[DebugInfo] Fix ARM/AArch64 prologue_end position. Related to D11268.

[oota-llvm.git] / lib / Target / Mips / Mips16ISelDAGToDAG.cpp

diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index bce2c1eb448595b86b79c592016c9e30c7898a0c..f471464b904178c80521b88c32dc8a2972eaeae3 100644 (file)
--- a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -70,13 +70,13 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
     return;
 
   MachineBasicBlock &MBB = MF.front();
-  MachineBasicBlock::iterator I = MBB.begin();
-  MachineRegisterInfo &RegInfo = MF.getRegInfo();
-  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
-  unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
-  const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
-
+  MachineBasicBlock::iterator I = MBB.begin();\r
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();\r
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();\r
+  DebugLoc DL;\r
+  unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();\r
+  const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;\r
+\r
   V0 = RegInfo.createVirtualRegister(RC);
   V1 = RegInfo.createVirtualRegister(RC);
   V2 = RegInfo.createVirtualRegister(RC);