Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."

[oota-llvm.git] / lib / Target / MSP430 / MSP430RegisterInfo.td

diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index 4078626ea2ddda0f0ea8c13191bd345710ef25d2..f488f00913865ad87c921f0b2d87cddd6db36a56 100644 (file)
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -60,12 +60,12 @@ def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
 def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
 def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
 
-def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
-                    R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
-                   [PCB, SPB, SRB, CGB, FPB,
-                    R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
 
-def subreg_8bit : PatLeaf<(i32 1)>;
+def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W,
+                              R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+                             [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B,
+                              R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
 
 def GR8 : RegisterClass<"MSP430", [i8], 8,
    // Volatile registers
@@ -101,7 +101,7 @@ def GR16 : RegisterClass<"MSP430", [i16], 16,
    // Volatile, but not allocable
    PCW, SPW, SRW, CGW]>
 {
-  let SubRegClassList = [GR8];
+  let SubRegClasses = [(GR8 subreg_8bit)];
   let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];