def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
-def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
- SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
-def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
- SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
-def SDT_MSP430Select : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisVT<3, i8>, SDTCisVT<4, i16>]>;
+def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
+ SDTCisVT<1, i8>]>;
+def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
+ SDTCisVT<3, i8>]>;
//===----------------------------------------------------------------------===//
// MSP430 Specific Node Definitions.
[SDNPHasChain, SDNPOptInFlag]>;
def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
+def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
+def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>;
def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
-def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
-def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
-def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
-def MSP430select : SDNode<"MSP430ISD::SELECT", SDT_MSP430Select>;
+def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutFlag]>;
+def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, [SDNPHasChain, SDNPInFlag]>;
+def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, [SDNPInFlag]>;
//===----------------------------------------------------------------------===//
// MSP430 Operand Definitions.
}
// Branch targets have OtherVT type.
-def brtarget : Operand<OtherVT>;
+def brtarget : Operand<OtherVT> {
+ let PrintMethod = "printPCRelImmOperand";
+}
// Operand for printing out a condition code.
def cc : Operand<i8> {
[(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
}
-let usesCustomDAGSchedInserter = 1 in {
+let usesCustomInserter = 1 in {
+ def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc),
+ "# Select8 PSEUDO",
+ [(set GR8:$dst,
+ (MSP430selectcc GR8:$src1, GR8:$src2, imm:$cc))]>;
def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
"# Select16 PSEUDO",
[(set GR16:$dst,
- (MSP430select GR16:$src1, GR16:$src2, imm:$cc, SRW))]>;
+ (MSP430selectcc GR16:$src1, GR16:$src2, imm:$cc))]>;
}
let neverHasSideEffects = 1 in
let Uses = [SRW] in
def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
"j$cc $dst",
- [(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
+ [(MSP430brcc bb:$dst, imm:$cc)]>;
} // isBranch, isTerminator
//===----------------------------------------------------------------------===//
let Defs = [R12W, R13W, R14W, R15W, SRW],
Uses = [SPW] in {
def CALLi : Pseudo<(outs), (ins i16imm:$dst, variable_ops),
- "call\t${dst:call}", [(MSP430call imm:$dst)]>;
+ "call\t$dst", [(MSP430call imm:$dst)]>;
def CALLr : Pseudo<(outs), (ins GR16:$dst, variable_ops),
"call\t$dst", [(MSP430call GR16:$dst)]>;
def CALLm : Pseudo<(outs), (ins memsrc:$dst, variable_ops),
"mov.b\t{$src, $dst}",
[(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
+def MOV8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR16:$base),
+ "mov.b\t{@$base+, $dst}", []>;
+def MOV16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$base),
+ "mov.w\t{@$base+, $dst}", []>;
+}
+
+// Any instruction that defines a 8-bit result leaves the high half of the
+// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
+// be copying from a truncate, but any other 8-bit operation will zero-extend
+// up to 16 bits.
+def def8 : PatLeaf<(i8 GR8:$src), [{
+ return N->getOpcode() != ISD::TRUNCATE &&
+ N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
+ N->getOpcode() != ISD::CopyFromReg;
+}]>;
+
+// In the case of a 8-bit def that is known to implicitly zero-extend,
+// we can use a SUBREG_TO_REG.
+def : Pat<(i16 (zext def8:$src)),
+ (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
+
+
def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
"mov.b\t{$src, $dst}",
[(store (i8 imm:$src), addr:$dst)]>;
"mov.w\t{$src, $dst}",
[(store GR16:$src, addr:$dst)]>;
+def MOV8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
+ "mov.b\t{$src, $dst}",
+ [(store (i8 (load addr:$src)), addr:$dst)]>;
+def MOV16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
+ "mov.w\t{$src, $dst}",
+ [(store (i16 (load addr:$src)), addr:$dst)]>;
+
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
[(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
(implicit SRW)]>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1,
+Constraints = "$base = $base_wb, $src1 = $dst" in {
+def ADD8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
+ "add.b\t{@$base+, $dst}", []>;
+def ADD16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
+ "add.w\t{@$base+, $dst}", []>;
+}
+
+
def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
"add.b\t{$src2, $dst}",
[(set GR8:$dst, (add GR8:$src1, imm:$src2)),
[(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
(implicit SRW)]>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1,
+Constraints = "$base = $base_wb, $src1 = $dst" in {
+def AND8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
+ "and.b\t{@$base+, $dst}", []>;
+def AND16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
+ "and.w\t{@$base+, $dst}", []>;
+}
+
let isTwoAddress = 0 in {
def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"and.b\t{$src, $dst}",
[(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
(implicit SRW)]>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1,
+Constraints = "$base = $base_wb, $src1 = $dst" in {
+def XOR8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
+ "xor.b\t{@$base+, $dst}", []>;
+def XOR16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
+ "xor.w\t{@$base+, $dst}", []>;
+}
+
let isTwoAddress = 0 in {
def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"xor.b\t{$src, $dst}",
[(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
(implicit SRW)]>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1,
+Constraints = "$base = $base_wb, $src1 = $dst" in {
+def SUB8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
+ "sub.b\t{@$base+, $dst}", []>;
+def SUB16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
+ "sub.w\t{@$base+, $dst}", []>;
+}
+
let isTwoAddress = 0 in {
def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"sub.b\t{$src, $dst}",
} // Uses = [SRW]
// FIXME: Provide proper encoding!
+def SAR8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
+ "rra.b\t$dst",
+ [(set GR8:$dst, (MSP430rra GR8:$src)),
+ (implicit SRW)]>;
def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"rra.w\t$dst",
[(set GR16:$dst, (MSP430rra GR16:$src)),
(implicit SRW)]>;
+def SHL8r1 : Pseudo<(outs GR8:$dst), (ins GR8:$src),
+ "rla.b\t$dst",
+ [(set GR8:$dst, (MSP430rla GR8:$src)),
+ (implicit SRW)]>;
+def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+ "rla.w\t$dst",
+ [(set GR16:$dst, (MSP430rla GR16:$src)),
+ (implicit SRW)]>;
+
+def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
+ "clrc\n\t"
+ "rrc.b\t$dst",
+ [(set GR8:$dst, (MSP430rrc GR8:$src)),
+ (implicit SRW)]>;
+def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+ "clrc\n\t"
+ "rrc.w\t$dst",
+ [(set GR16:$dst, (MSP430rrc GR16:$src)),
+ (implicit SRW)]>;
+
def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"sxt\t$dst",
[(set GR16:$dst, (sext_inreg GR16:$src, i8)),
(implicit SRW)]>;
-//def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
-// "sxt\t$dst",
-// [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
-// (implicit SRW)]>;
-
} // Defs = [SRW]
+def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+ "swpb\t$dst",
+ [(set GR16:$dst, (bswap GR16:$src))]>;
+
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"bis.b\t{$src2, $dst}",
"bis.w\t{$src2, $dst}",
[(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
+let mayLoad = 1, hasExtraDefRegAllocReq = 1,
+Constraints = "$base = $base_wb, $src1 = $dst" in {
+def OR8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR8:$src1, GR16:$base),
+ "bis.b\t{@$base+, $dst}", []>;
+def OR16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$src1, GR16:$base),
+ "bis.w\t{@$base+, $dst}", []>;
+}
+
let isTwoAddress = 0 in {
def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"bis.b\t{$src, $dst}",
- [(store (or (load addr:$dst), GR8:$src), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
"bis.w\t{$src, $dst}",
- [(store (or (load addr:$dst), GR16:$src), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
"bis.b\t{$src, $dst}",
- [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
"bis.w\t{$src, $dst}",
- [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bis.b\t{$src, $dst}",
- [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (i8 (load addr:$dst)),
+ (i8 (load addr:$src))), addr:$dst)]>;
def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bis.w\t{$src, $dst}",
- [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (i16 (load addr:$dst)),
+ (i16 (load addr:$src))), addr:$dst)]>;
}
} // isTwoAddress = 1
"cmp.w\t{$src1, $src2}",
[(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
-def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
+def CMP8ir : Pseudo<(outs), (ins i8imm:$src1, GR8:$src2),
+ "cmp.b\t{$src1, $src2}",
+ [(MSP430cmp imm:$src1, GR8:$src2), (implicit SRW)]>;
+def CMP16ir : Pseudo<(outs), (ins i16imm:$src1, GR16:$src2),
+ "cmp.w\t{$src1, $src2}",
+ [(MSP430cmp imm:$src1, GR16:$src2), (implicit SRW)]>;
+
+def CMP8im : Pseudo<(outs), (ins i8imm:$src1, memsrc:$src2),
"cmp.b\t{$src1, $src2}",
- [(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
-def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
+ [(MSP430cmp (i8 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
+def CMP16im : Pseudo<(outs), (ins i16imm:$src1, memsrc:$src2),
"cmp.w\t{$src1, $src2}",
- [(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
+ [(MSP430cmp (i16 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
"cmp.b\t{$src1, $src2}",
"cmp.w\t{$src1, $src2}",
[(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
-def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
- "cmp.b\t{$src1, $src2}",
- [(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
-def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
- "cmp.w\t{$src1, $src2}",
- [(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
+def CMP8mi0 : Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.b\t{$src1, #0}",
+ [(MSP430cmp (load addr:$src1), (i8 0)), (implicit SRW)]>;
+def CMP16mi0: Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.w\t{$src1, #0}",
+ [(MSP430cmp (load addr:$src1), (i16 0)), (implicit SRW)]>;
+def CMP8mi1 : Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.b\t{$src1, #1}",
+ [(MSP430cmp (load addr:$src1), (i8 1)), (implicit SRW)]>;
+def CMP16mi1: Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.w\t{$src1, #1}",
+ [(MSP430cmp (load addr:$src1), (i16 1)), (implicit SRW)]>;
+def CMP8mi2 : Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.b\t{$src1, #2}",
+ [(MSP430cmp (load addr:$src1), (i8 2)), (implicit SRW)]>;
+def CMP16mi2: Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.w\t{$src1, #2}",
+ [(MSP430cmp (load addr:$src1), (i16 2)), (implicit SRW)]>;
+def CMP8mi4 : Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.b\t{$src1, #4}",
+ [(MSP430cmp (load addr:$src1), (i8 4)), (implicit SRW)]>;
+def CMP16mi4: Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.w\t{$src1, #4}",
+ [(MSP430cmp (load addr:$src1), (i16 4)), (implicit SRW)]>;
+def CMP8mi8 : Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.b\t{$src1, #8}",
+ [(MSP430cmp (load addr:$src1), (i8 8)), (implicit SRW)]>;
+def CMP16mi8: Pseudo<(outs), (ins memsrc:$src1),
+ "cmp.w\t{$src1, #8}",
+ [(MSP430cmp (load addr:$src1), (i16 8)), (implicit SRW)]>;
-def CMP8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
- "cmp.b\t{$src1, $src2}",
- [(MSP430cmp (load addr:$src1), (i8 (load addr:$src2))), (implicit SRW)]>;
-def CMP16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
- "cmp.w\t{$src1, $src2}",
- [(MSP430cmp (load addr:$src1), (i16 (load addr:$src2))), (implicit SRW)]>;
} // Defs = [SRW]
//===----------------------------------------------------------------------===//
// extload
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
+// anyext
+def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>;
+
// truncs
def : Pat<(i8 (trunc GR16:$src)),
(EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
-// GlobalAddress
+// GlobalAddress, ExternalSymbol
def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>;
+def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>;
def : Pat<(add GR16:$src1, (MSP430Wrapper tglobaladdr :$src2)),
(ADD16ri GR16:$src1, tglobaladdr:$src2)>;
+def : Pat<(add GR16:$src1, (MSP430Wrapper texternalsym:$src2)),
+ (ADD16ri GR16:$src1, texternalsym:$src2)>;
+
+def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst),
+ (MOV16mi addr:$dst, tglobaladdr:$src)>;
+def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst),
+ (MOV16mi addr:$dst, texternalsym:$src)>;
// calls
def : Pat<(MSP430call (i16 tglobaladdr:$dst)),
(CALLi tglobaladdr:$dst)>;
+def : Pat<(MSP430call (i16 texternalsym:$dst)),
+ (CALLi texternalsym:$dst)>;
+
+// add and sub always produce carry
+def : Pat<(addc GR16:$src1, GR16:$src2),
+ (ADD16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(addc GR16:$src1, (load addr:$src2)),
+ (ADD16rm GR16:$src1, addr:$src2)>;
+def : Pat<(addc GR16:$src1, imm:$src2),
+ (ADD16ri GR16:$src1, imm:$src2)>;
+def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst),
+ (ADD16mr addr:$dst, GR16:$src)>;
+def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
+ (ADD16mm addr:$dst, addr:$src)>;
+
+def : Pat<(addc GR8:$src1, GR8:$src2),
+ (ADD8rr GR8:$src1, GR8:$src2)>;
+def : Pat<(addc GR8:$src1, (load addr:$src2)),
+ (ADD8rm GR8:$src1, addr:$src2)>;
+def : Pat<(addc GR8:$src1, imm:$src2),
+ (ADD8ri GR8:$src1, imm:$src2)>;
+def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst),
+ (ADD8mr addr:$dst, GR8:$src)>;
+def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
+ (ADD8mm addr:$dst, addr:$src)>;
+
+def : Pat<(subc GR16:$src1, GR16:$src2),
+ (SUB16rr GR16:$src1, GR16:$src2)>;
+def : Pat<(subc GR16:$src1, (load addr:$src2)),
+ (SUB16rm GR16:$src1, addr:$src2)>;
+def : Pat<(subc GR16:$src1, imm:$src2),
+ (SUB16ri GR16:$src1, imm:$src2)>;
+def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst),
+ (SUB16mr addr:$dst, GR16:$src)>;
+def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
+ (SUB16mm addr:$dst, addr:$src)>;
+
+def : Pat<(subc GR8:$src1, GR8:$src2),
+ (SUB8rr GR8:$src1, GR8:$src2)>;
+def : Pat<(subc GR8:$src1, (load addr:$src2)),
+ (SUB8rm GR8:$src1, addr:$src2)>;
+def : Pat<(subc GR8:$src1, imm:$src2),
+ (SUB8ri GR8:$src1, imm:$src2)>;
+def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst),
+ (SUB8mr addr:$dst, GR8:$src)>;
+def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
+ (SUB8mm addr:$dst, addr:$src)>;
projects / oota-llvm.git / blobdiff