Added InstrSchedClass to each of the PowerPC Instructions.

[oota-llvm.git] / lib / Target / MRegisterInfo.cpp

diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 7c1028bc32379834f7e77fb5819c4a94cedabadf..c8eba554dbca7923fda5ab68522d27739b12872d 100644 (file)
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -1,10 +1,10 @@
 //===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements the MRegisterInfo interface.
@@ -15,33 +15,29 @@
 
 namespace llvm {
 
-MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
+MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
                              regclass_iterator RCB, regclass_iterator RCE,
-                            int CFSO, int CFDO)
+                             int CFSO, int CFDO)
   : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
   assert(NumRegs < FirstVirtualRegister &&
          "Target has too many physical registers!");
 
-  PhysRegClasses = new const TargetRegisterClass*[NumRegs];
-  for (unsigned i = 0; i != NumRegs; ++i)
-    PhysRegClasses[i] = 0;
-
-  // Fill in the PhysRegClasses map
-  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
-         E = regclass_end(); I != E; ++I)
-    for (unsigned i = 0, e = (*I)->getNumRegs(); i != e; ++i) {
-      unsigned Reg = (*I)->getRegister(i);
-      assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?");
-      PhysRegClasses[Reg] = *I;
-    }
-
   CallFrameSetupOpcode   = CFSO;
   CallFrameDestroyOpcode = CFDO;
 }
 
+MRegisterInfo::~MRegisterInfo() {}
 
-MRegisterInfo::~MRegisterInfo() {
-  delete[] PhysRegClasses;
+std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
+  std::vector<bool> Allocatable(NumRegs);
+  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
+         E = regclass_end(); I != E; ++I) {
+    const TargetRegisterClass *RC = *I;
+    for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+           E = RC->allocation_order_end(MF); I != E; ++I)
+      Allocatable[*I] = true;
+  }
+  return Allocatable;
 }
 
 } // End llvm namespace