#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
-#include <iostream>
using namespace llvm;
-
-IA64RegisterInfo::IA64RegisterInfo()
- : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {}
+IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
+ : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
+ TII(tii) {}
void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const TargetRegisterClass *RC) const{
if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
+ BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
+ .addReg(SrcReg, false, false, true);
} else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
- }
- else if (RC == IA64::PRRegisterClass) {
+ BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
+ .addReg(SrcReg, false, false, true);
+ } else if (RC == IA64::PRRegisterClass) {
/* we use IA64::r2 as a temporary register for doing this hackery. */
// first we load 0:
- BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0);
+ BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
// then conditionally add 1:
- BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2)
- .addImm(1).addReg(SrcReg);
+ BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
+ .addImm(1).addReg(SrcReg, false, false, true);
// and then store it to the stack
- BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2);
+ BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
} else assert(0 &&
"sorry, I don't know how to store this sort of reg in the stack\n");
}
const TargetRegisterClass *RC)const{
if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
+ BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
+ BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::PRRegisterClass) {
// first we load a byte from the stack into r2, our 'predicate hackery'
// scratch reg
- BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx);
+ BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
// then we compare it to zero. If it _is_ zero, compare-not-equal to
// r0 gives us 0, which is what we want, so that's nice.
- BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0);
+ BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
} else assert(0 &&
"sorry, I don't know how to load this sort of reg from the stack\n");
}
if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
// (SrcReg) DestReg = cmp.eq.unc(r0, r0)
- BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
+ BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg)
+ .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs)
- BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
+}
+
+const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
+ static const unsigned CalleeSavedRegs[] = {
+ IA64::r5, 0
+ };
+ return CalleeSavedRegs;
+}
+
+const TargetRegisterClass* const*
+IA64RegisterInfo::getCalleeSavedRegClasses() const {
+ static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
+ &IA64::GRRegClass, 0
+ };
+ return CalleeSavedRegClasses;
+}
+
+BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ Reserved.set(IA64::r0);
+ Reserved.set(IA64::r1);
+ Reserved.set(IA64::r2);
+ Reserved.set(IA64::r5);
+ Reserved.set(IA64::r12);
+ Reserved.set(IA64::r13);
+ Reserved.set(IA64::r22);
+ Reserved.set(IA64::rp);
+ return Reserved;
}
//===----------------------------------------------------------------------===//
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
-static bool hasFP(MachineFunction &MF) {
+bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
void IA64RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
-
if (hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
MachineInstr *New;
if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
- New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
+ New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
.addImm(-Amount);
} else {
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
- New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
+ New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
.addImm(Amount);
}
MBB.erase(I);
}
-void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
+void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ RegScavenger *RS)const{
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
// choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
// Add the base register
- MI.SetMachineOperandReg(i, BaseRegister);
+ MI.getOperand(i).ChangeToRegister(BaseRegister, false);
// Now add the frame object offset to the offset from r1.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
Offset += MF.getFrameInfo()->getStackSize();
// XXX: we use 'r22' as another hack+slash temporary register here :(
- if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
- //fix up the old:
- MI.SetMachineOperandReg(i, IA64::r22);
- MI.getOperand(i).setUse(); // mark r22 as being used
- // (the bundler wants to know this)
+ if (Offset <= 8191 && Offset >= -8192) { // smallish offset
+ // Fix up the old:
+ MI.getOperand(i).ChangeToRegister(IA64::r22, false);
//insert the new
- MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
+ MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
.addReg(BaseRegister).addImm(Offset);
MBB.insert(II, nMI);
} else { // it's big
//fix up the old:
- MI.SetMachineOperandReg(i, IA64::r22);
- MI.getOperand(i).setUse(); // mark r22 as being used
- // (the bundler wants to know this)
+ MI.getOperand(i).ChangeToRegister(IA64::r22, false);
MachineInstr* nMI;
- nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
+ nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
MBB.insert(II, nMI);
- nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
+ nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
.addReg(IA64::r22);
MBB.insert(II, nMI);
}
unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
- // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB)
+ // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
+ // a pseudo_alloc in the MBB)
unsigned dstRegOfPseudoAlloc;
for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
assert(MBBI != MBB.end());
}
}
- MI=BuildMI(IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0).\
+ MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
MBB.insert(MBBI, MI);
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize();
- if (MFI->hasCalls() && !FP) {
- // We reserve argument space for call sites in the function immediately on
- // entry to the current function. This eliminates the need for add/sub
- // brackets around call sites.
- NumBytes += MFI->getMaxCallFrameSize();
- }
-
if(FP)
NumBytes += 8; // reserve space for the old FP
// adjust stack pointer: r12 -= numbytes
if (NumBytes <= 8191) {
- MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
+ MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
+ addImm(-NumBytes);
MBB.insert(MBBI, MI);
} else { // we use r22 as a scratch register here
- MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
+ MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
// FIXME: MOVLSI32 expects a _u_32imm
MBB.insert(MBBI, MI); // first load the decrement into r22
- MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
+ MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
}
// now if we need to, save the old FP and set the new
if (FP) {
- MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
+ MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
MBB.insert(MBBI, MI);
// this must be the last instr in the prolog ? (XXX: why??)
- MI = BuildMI(IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
+ MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
MBB.insert(MBBI, MI);
}
if (FP)
{
//copy the FP into the SP (discards allocas)
- MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
+ MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
MBB.insert(MBBI, MI);
//restore the FP
- MI=BuildMI(IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
+ MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
MBB.insert(MBBI, MI);
}
if (NumBytes != 0)
{
if (NumBytes <= 8191) {
- MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
+ MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
+ addImm(NumBytes);
MBB.insert(MBBI, MI);
} else {
- MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
+ MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
MBB.insert(MBBI, MI);
- MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
+ MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
+ addReg(IA64::r22);
MBB.insert(MBBI, MI);
}
}
return hasFP(MF) ? IA64::r5 : IA64::r12;
}
+unsigned IA64RegisterInfo::getEHExceptionRegister() const {
+ assert(0 && "What is the exception register");
+ return 0;
+}
+
+unsigned IA64RegisterInfo::getEHHandlerRegister() const {
+ assert(0 && "What is the exception handler register");
+ return 0;
+}
+
#include "IA64GenRegisterInfo.inc"
projects / oota-llvm.git / blobdiff