Added field noResults to Instruction.

[oota-llvm.git] / lib / Target / IA64 / IA64InstrInfo.td

diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index fc765d300deeddddb6a26066ff8567f3db787105..a38338ffca6f610f83eb4fcc63a5feb86fd8f712 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -15,6 +15,14 @@
 
 include "IA64InstrFormats.td"
 
+//===----------------------------------------------------------------------===//
+// IA-64 specific DAG Nodes.
+//
+
+def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
+
+//===---------
+
 def u2imm : Operand<i8>;
 def u6imm : Operand<i8>;
 def s8imm : Operand<i8> {
@@ -23,7 +31,7 @@ def s8imm : Operand<i8> {
 def s14imm  : Operand<i64> {
   let PrintMethod = "printS14ImmOperand";
 }
-def s22imm  : Operand<i32> {
+def s22imm  : Operand<i64> {
   let PrintMethod = "printS22ImmOperand";
 }
 def u64imm  : Operand<i64> {
@@ -116,7 +124,12 @@ def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
            "addl $dst = $imm, $src1;;",
           []>;
-  
+
+// hmm 
+def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
+           "addl $dst = $imm, $src1;;",
+          []>;
+ 
 def SUB  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2;;",
           [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
@@ -156,31 +169,31 @@ def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
 def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix1.l $dst = $src1, $src2;;",
          [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
-                            (and (srl GR:$src2, 8), isMIX1Lable)))]>;
+                            (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>;
 
 def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix2.l $dst = $src1, $src2;;",
          [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
-                            (and (srl GR:$src2, 16), isMIX2Lable)))]>;
+                            (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>;
 
 def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix4.l $dst = $src1, $src2;;",
          [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
-                            (and (srl GR:$src2, 32), isMIX4Lable)))]>;
+                            (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>;
 
 def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix1.r $dst = $src1, $src2;;",
-         [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable),
+         [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
                             (and GR:$src2, isMIX1Rable)))]>;
 
 def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix2.r $dst = $src1, $src2;;",
-         [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable),
+         [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
                             (and GR:$src2, isMIX2Rable)))]>;
 
 def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
           "mix4.r $dst = $src1, $src2;;",
-         [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
+         [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
                             (and GR:$src2, isMIX4Rable)))]>;
 
 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
@@ -388,6 +401,8 @@ def SHRS  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
          [(set GR:$dst, (sra GR:$src1, GR:$src2))]>;
 
 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
+def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+  "mov $dst = $src;;">; // XXX: there _is_ no fmov
 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
   "($qp) mov $dst = $src;;">;
 
@@ -409,9 +424,11 @@ let isTwoAddress = 1 in {
     "($qp) mov $dst = $src;;">;
 }
 
-// TODO: select FPs, bools
+// TODO: select bools
 def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
           (CMOV (MOV GR:$src2), GR:$src1, PR:$which)>; // note order!
+def SELECTFP : Pat<(select PR:$which, FP:$src1, FP:$src2),
+          (CFMOV (FMOV FP:$src2), FP:$src1, PR:$which)>; // note order!
 
 // load constants of various sizes // FIXME: prettyprint -ve constants
 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
@@ -503,7 +520,7 @@ def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
   "sub $dst = $imm, $src2;;">;
 
-let isStore = 1 in {
+let isStore = 1, noResults = 1 in {
   def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
     "st1 [$dstPtr] = $value;;">;
   def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
@@ -549,8 +566,6 @@ def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
 def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
   "fmpy $dst = $src1, $src2;;",
   [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>;
-def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
-  "mov $dst = $src;;">; // XXX: there _is_ no fmov
 def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "fma $dst = $src1, $src2, $src3;;",
   [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>;
@@ -628,7 +643,7 @@ def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
   (GETFSIG (FCVTFXUTRUNC FP:$src))>;
 
 
-let isTerminator = 1, isBranch = 1 in {
+let isTerminator = 1, isBranch = 1, noResults = 1 in {
   def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
     "(p0) brl.cond.sptk $dst;;">;
   def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
@@ -637,7 +652,7 @@ let isTerminator = 1, isBranch = 1 in {
     "($qp) br.cond.sptk $dst;;">;
 }
 
-let isCall = 1, isTerminator = 1, isBranch = 1, 
+let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
   Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
 // all calls clobber non-callee-saved registers, and for now, they are these:
   Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
@@ -657,9 +672,15 @@ let isCall = 1, isTerminator = 1, isBranch = 1,
   def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
   "br.call.sptk rp = $dst;;">;       // FIXME: teach llvm about branch regs?
 // new daggy stuff!  
-  def BRCALL_IPREL : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops),
+
+// calls a globaladdress
+  def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst),
+  "br.call.sptk rp = $dst;;">;       // FIXME: teach llvm about branch regs?
+// calls an externalsymbol
+  def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst),
   "br.call.sptk rp = $dst;;">;       // FIXME: teach llvm about branch regs?
-  def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg, variable_ops),
+// calls through a function descriptor
+  def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg),
   "br.call.sptk rp = $branchreg;;">; // FIXME: teach llvm about branch regs?
   def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
     "($qp) brl.cond.call.sptk $dst;;">;
@@ -667,7 +688,7 @@ let isCall = 1, isTerminator = 1, isBranch = 1,
     "($qp) br.cond.call.sptk $dst;;">;
 }
 
-let isTerminator = 1, isReturn = 1 in
+let isTerminator = 1, isReturn = 1, noResults = 1 in
   def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return