Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and...

[oota-llvm.git] / lib / Target / IA64 / IA64ISelLowering.cpp

diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index b6b6c256e4e113249ddb975f5bb42cec08e75f57..e4d4867888e902b397d7c4004c25600a5aff9dd6 100644 (file)
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -37,9 +37,9 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
 
       setLoadXAction(ISD::EXTLOAD          , MVT::i1   , Promote);
 
-      setLoadXAction(ISD::ZEXTLOAD         , MVT::i1   , Expand);
+      setLoadXAction(ISD::ZEXTLOAD         , MVT::i1   , Promote);
 
-      setLoadXAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
+      setLoadXAction(ISD::SEXTLOAD         , MVT::i1   , Promote);
       setLoadXAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
       setLoadXAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
       setLoadXAction(ISD::SEXTLOAD         , MVT::i32  , Expand);
@@ -69,7 +69,8 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
       setOperationAction(ISD::MEMMOVE          , MVT::Other, Expand);
       setOperationAction(ISD::MEMSET           , MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY           , MVT::Other, Expand);
-      
+      setOperationAction(ISD::MEMBARRIER       , MVT::Other, Expand);
+
       setOperationAction(ISD::SINT_TO_FP       , MVT::i1   , Promote);
       setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
 
@@ -109,6 +110,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
       setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
       setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
       setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+      setOperationAction(ISD::PREFETCH          , MVT::Other, Expand);
 
       // Thread Local Storage
       setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
@@ -120,11 +122,10 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
       
       computeRegisterProperties();
 
-      setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
       addLegalFPImmediate(APFloat(+0.0));
-      addLegalFPImmediate(APFloat(+0.0f));
+      addLegalFPImmediate(APFloat(-0.0));
       addLegalFPImmediate(APFloat(+1.0));
-      addLegalFPImmediate(APFloat(+1.0f));
+      addLegalFPImmediate(APFloat(-1.0));
 }
 
 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -193,7 +194,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
             argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
                                                 MVT::f64);
             if (I->getType() == Type::FloatTy)
-              argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
+              argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
+                                 DAG.getIntPtrConstant(0));
             break;
           case MVT::i1: // NOTE: as far as C abi stuff goes,
                         // bools are just boring old ints
@@ -298,8 +300,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
 }
 
 std::pair<SDOperand, SDOperand>
-IA64TargetLowering::LowerCallTo(SDOperand Chain,
-                                const Type *RetTy, bool RetTyIsSigned, 
+IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+                                bool RetSExt, bool RetZExt,
                                 bool isVarArg, unsigned CallingConv, 
                                 bool isTailCall, SDOperand Callee, 
                                 ArgListTy &Args, SelectionDAG &DAG) {
@@ -580,16 +582,16 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   }
   case ISD::VAARG: {
     MVT::ValueType VT = getPointerTy();
-    SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
+    const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
     SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), 
-                                   SV->getValue(), SV->getOffset());
+                                   SV, 0);
     // Increment the pointer, VAList, to the next vaarg
     SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, 
                                    DAG.getConstant(MVT::getSizeInBits(VT)/8, 
                                                    VT));
     // Store the incremented VAList to the legalized pointer
     VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
-                          Op.getOperand(1), SV->getValue(), SV->getOffset());
+                          Op.getOperand(1), SV, 0);
     // Load the actual argument out of the pointer VAList
     return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
   }
@@ -597,9 +599,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     // vastart just stores the address of the VarArgsFrameIndex slot into the
     // memory location argument.
     SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
-    SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
-    return DAG.getStore(Op.getOperand(0), FR, 
-                        Op.getOperand(1), SV->getValue(), SV->getOffset());
+    const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
+    return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
   }
   // Frame & Return address.  Currently unimplemented
   case ISD::RETURNADDR:         break;