Fix PR1749 and InstCombine/2007-10-28-EmptyField.ll by handling

[oota-llvm.git] / lib / Target / IA64 / IA64ISelLowering.cpp

diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 9a1c57bace3658ae29476dc720520a5b22c56eb2..82cbd9c2118faff99916cc410035f4211ce49bb3 100644 (file)
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -73,13 +73,15 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
       setOperationAction(ISD::SINT_TO_FP       , MVT::i1   , Promote);
       setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
 
-      // We don't support sin/cos/sqrt
+      // We don't support sin/cos/sqrt/pow
       setOperationAction(ISD::FSIN , MVT::f64, Expand);
       setOperationAction(ISD::FCOS , MVT::f64, Expand);
       setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+      setOperationAction(ISD::FPOW , MVT::f64, Expand);
       setOperationAction(ISD::FSIN , MVT::f32, Expand);
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+      setOperationAction(ISD::FPOW , MVT::f32, Expand);
 
       // FIXME: IA64 supports fcopysign natively!
       setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
@@ -108,6 +110,9 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
       setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
       setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
 
+      // Thread Local Storage
+      setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+
       setStackPointerRegisterToSaveRestore(IA64::r12);
 
       setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
@@ -116,8 +121,10 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
       computeRegisterProperties();
 
       setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
-      addLegalFPImmediate(+0.0);
-      addLegalFPImmediate(+1.0);
+      addLegalFPImmediate(APFloat(+0.0));
+      addLegalFPImmediate(APFloat(+0.0f));
+      addLegalFPImmediate(APFloat(+1.0));
+      addLegalFPImmediate(APFloat(+1.0f));
 }
 
 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -341,9 +348,11 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
       case MVT::i32: {
         //promote to 64-bits, sign/zero extending based on type
         //of the argument
-        ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
-        if (Args[i].isSigned)
+        ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
+        if (Args[i].isSExt)
           ExtendKind = ISD::SIGN_EXTEND;
+        else if (Args[i].isZExt)
+          ExtendKind = ISD::ZERO_EXTEND;
         Val = DAG.getNode(ExtendKind, MVT::i64, Val);
         // XXX: fall through
       }
@@ -364,9 +373,9 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
           ValToStore = Val;
         } else {
           RegValuesToPass.push_back(Val);
-         if(1 /* TODO: if(calling external or varadic function)*/ ) {
-           ValToConvert = Val; // additionally pass this FP value as an int
-         }
+          if(1 /* TODO: if(calling external or varadic function)*/ ) {
+            ValToConvert = Val; // additionally pass this FP value as an int
+          }
         }
         break;
       }
@@ -382,7 +391,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
       }
 
       if(ValToConvert.Val) {
-       Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
+        Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
       }
     }
 
@@ -490,7 +499,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
       Chain = boolInR8.getValue(1);
       SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
       InFlag = zeroReg.getValue(2);
-      Chain = zeroReg.getValue(1);     
+      Chain = zeroReg.getValue(1);
       
       RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
       break;
@@ -536,6 +545,8 @@ SDOperand IA64TargetLowering::
 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default: assert(0 && "Should not custom lower this!");
+  case ISD::GlobalTLSAddress:
+    assert(0 && "TLS not implemented for IA64.");
   case ISD::RET: {
     SDOperand AR_PFSVal, Copy;
     
@@ -590,9 +601,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   // Frame & Return address.  Currently unimplemented
   case ISD::RETURNADDR:         break;
   case ISD::FRAMEADDR:          break;
-  // Exception address and exception selector.  Currently unimplemented.
-  case ISD::EXCEPTIONADDR: break;
-  case ISD::EHSELECTION:   break;
   }
   return SDOperand();
 }