#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include <queue>
-#include <set>
using namespace llvm;
namespace {
/// instructions for SelectionDAG operations.
///
class IA64DAGToDAGISel : public SelectionDAGISel {
- IA64TargetLowering IA64Lowering;
unsigned GlobalBaseReg;
public:
explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
- : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
+ : SelectionDAGISel(TM) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
DEBUG(BB->dump());
// Select target instructions for the DAG.
- SelectRoot();
+ SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
SDValue Chain = N->getOperand(0);
SDValue Tmp1 = N->getOperand(0);
SDValue Tmp2 = N->getOperand(1);
- AddToISelQueue(Chain);
-
- AddToISelQueue(Tmp1);
- AddToISelQueue(Tmp2);
bool isFP=false;
SDValue Chain = N->getOperand(0);
SDValue InFlag; // Null incoming flag value.
- AddToISelQueue(Chain);
if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
InFlag = N->getOperand(2);
- AddToISelQueue(InFlag);
}
unsigned CallOpcode;
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
SDValue FnDescriptor = N->getOperand(1);
- AddToISelQueue(FnDescriptor);
// load the branch target's entry point [mem] and
// GP value [mem+8]
Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
InFlag = Chain.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
+ Chain = CurDAG->getCopyToReg(Chain, IA64::B6,
+ targetEntryPoint, InFlag); // FLAG these?
InFlag = Chain.getValue(1);
CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
case IA64ISD::GETFD: {
SDValue Input = N->getOperand(0);
- AddToISelQueue(Input);
return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
}
LoadSDNode *LD = cast<LoadSDNode>(N);
SDValue Chain = LD->getChain();
SDValue Address = LD->getBasePtr();
- AddToISelQueue(Chain);
- AddToISelQueue(Address);
MVT TypeBeingLoaded = LD->getMemoryVT();
unsigned Opc;
StoreSDNode *ST = cast<StoreSDNode>(N);
SDValue Address = ST->getBasePtr();
SDValue Chain = ST->getChain();
- AddToISelQueue(Address);
- AddToISelQueue(Chain);
unsigned Opc;
if (ISD::isNON_TRUNCStore(N)) {
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
SDValue Tmp = ST->getValue();
- AddToISelQueue(Tmp);
Tmp =
SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
- CurDAG->getTargetConstant(1, MVT::i64),
+ CurDAG->getTargetConstant(1,
+ MVT::i64),
Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
- AddToISelQueue(N1);
- AddToISelQueue(N2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
SDValue Chain = N->getOperand(0);
SDValue CC = N->getOperand(1);
- AddToISelQueue(Chain);
- AddToISelQueue(CC);
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END: {
- int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
+ int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDValue N0 = N->getOperand(0);
- AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
SDValue N0 = N->getOperand(0);
- AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0);
}