//
// Note: The peephole pass makes the instrucstions like
// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
-// redundant and relies on some form of dead removal instrucions, like
+// redundant and relies on some form of dead removal instructions, like
// DCE or DIE to actually eliminate them.
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "hexagon-peephole"
#include "Hexagon.h"
#include "HexagonTargetMachine.h"
#include "llvm/ADT/DenseMap.h"
using namespace llvm;
+#define DEBUG_TYPE "hexagon-peephole"
+
static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Peephole Optimization"));
initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
}
- bool runOnMachineFunction(MachineFunction &MF);
+ bool runOnMachineFunction(MachineFunction &MF) override;
- const char *getPassName() const {
+ const char *getPassName() const override {
return "Hexagon optimize redundant zero and size extends";
}
- void getAnalysisUsage(AnalysisUsage &AU) const {
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU);
}
false, false)
bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
- QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().
- getInstrInfo());
- QRI = static_cast<const HexagonRegisterInfo *>(MF.getTarget().
- getRegisterInfo());
+ QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
+ QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
MRI = &MF.getRegInfo();
DenseMap<unsigned, unsigned> PeepholeMap;
MachineInstr *MI = MII;
// Look for sign extends:
// %vreg170<def> = SXTW %vreg166
- if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
+ if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) {
assert (MI->getNumOperands() == 2);
MachineOperand &Dst = MI->getOperand(0);
MachineOperand &Src = MI->getOperand(1);
// Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
// %vreg170:DoublRegs, %vreg169:IntRegs
if (!DisableOptExtTo64 &&
- MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
+ MI->getOpcode () == Hexagon::A4_combineir) {
assert (MI->getNumOperands() == 3);
MachineOperand &Dst = MI->getOperand(0);
MachineOperand &Src1 = MI->getOperand(1);
// %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
// and convert into
// %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
- if (MI->getOpcode() == Hexagon::LSRd_ri) {
+ if (MI->getOpcode() == Hexagon::S2_lsr_i_p) {
assert(MI->getNumOperands() == 3);
MachineOperand &Dst = MI->getOperand(0);
MachineOperand &Src1 = MI->getOperand(1);
// Look for P=NOT(P).
if (!DisablePNotP &&
- (MI->getOpcode() == Hexagon::NOT_p)) {
+ (MI->getOpcode() == Hexagon::C2_not)) {
assert (MI->getNumOperands() == 2);
MachineOperand &Dst = MI->getOperand(0);
MachineOperand &Src = MI->getOperand(1);
unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
switch (Op) {
- case Hexagon::TFR_condset_rr:
- case Hexagon::TFR_condset_ii:
- case Hexagon::MUX_ii:
- case Hexagon::MUX_rr:
+ case Hexagon::C2_mux:
+ case Hexagon::C2_muxii:
NewOp = Op;
break;
- case Hexagon::TFR_condset_ri:
- NewOp = Hexagon::TFR_condset_ir;
- break;
- case Hexagon::TFR_condset_ir:
- NewOp = Hexagon::TFR_condset_ri;
- break;
- case Hexagon::MUX_ri:
- NewOp = Hexagon::MUX_ir;
+ case Hexagon::C2_muxri:
+ NewOp = Hexagon::C2_muxir;
break;
- case Hexagon::MUX_ir:
- NewOp = Hexagon::MUX_ri;
+ case Hexagon::C2_muxir:
+ NewOp = Hexagon::C2_muxri;
break;
}
if (NewOp) {