[Hexagon] Updating predicate register transfers and adding tstbit to allow select...

[oota-llvm.git] / lib / Target / Hexagon / HexagonInstrInfoV4.td

diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td
index 6b8ce21daa9a365900de9f6ae611de4ba15188e4..4241decc89996b635e024268ca21c5c4097bd7a5 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -3016,7 +3016,7 @@ def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),
 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
 let AddedComplexity = 100 in
 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
-           (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
+           (i1 (C2_tfrrp (i32 (LDb_GP_V4 tglobaladdr:$global))))>;
 
 // When the Interprocedural Global Variable optimizer realizes that a certain
 // global variable takes only two constant values, it shrinks the global to