SrcReg = MI->getOperand(1).getReg();
Mask = ~0;
break;
- case Hexagon::CMPbEQri_V4:
- case Hexagon::CMPbEQrr_sbsb_V4:
- case Hexagon::CMPbEQrr_ubub_V4:
- case Hexagon::CMPbGTUri_V4:
- case Hexagon::CMPbGTUrr_V4:
- case Hexagon::CMPbGTrr_V4:
+ case Hexagon::A4_cmpbeqi:
+ case Hexagon::A4_cmpbeq:
+ case Hexagon::A4_cmpbgtui:
+ case Hexagon::A4_cmpbgtu:
+ case Hexagon::A4_cmpbgt:
SrcReg = MI->getOperand(1).getReg();
Mask = 0xFF;
break;
- case Hexagon::CMPhEQri_V4:
- case Hexagon::CMPhEQrr_shl_V4:
- case Hexagon::CMPhEQrr_xor_V4:
- case Hexagon::CMPhGTUri_V4:
- case Hexagon::CMPhGTUrr_V4:
- case Hexagon::CMPhGTrr_shl_V4:
+ case Hexagon::A4_cmpheqi:
+ case Hexagon::A4_cmpheq:
+ case Hexagon::A4_cmphgtui:
+ case Hexagon::A4_cmphgtu:
+ case Hexagon::A4_cmphgt:
SrcReg = MI->getOperand(1).getReg();
Mask = 0xFFFF;
break;
case Hexagon::C2_cmpgtup:
case Hexagon::C2_cmpgtu:
case Hexagon::C2_cmpgt:
- case Hexagon::CMPbEQrr_sbsb_V4:
- case Hexagon::CMPbEQrr_ubub_V4:
- case Hexagon::CMPbGTUrr_V4:
- case Hexagon::CMPbGTrr_V4:
- case Hexagon::CMPhEQrr_shl_V4:
- case Hexagon::CMPhEQrr_xor_V4:
- case Hexagon::CMPhGTUrr_V4:
- case Hexagon::CMPhGTrr_shl_V4:
+ case Hexagon::A4_cmpbeq:
+ case Hexagon::A4_cmpbgtu:
+ case Hexagon::A4_cmpbgt:
+ case Hexagon::A4_cmpheq:
+ case Hexagon::A4_cmphgtu:
+ case Hexagon::A4_cmphgt:
SrcReg2 = MI->getOperand(2).getReg();
return true;
case Hexagon::C2_cmpeqi:
case Hexagon::C2_cmpgtui:
case Hexagon::C2_cmpgti:
- case Hexagon::CMPbEQri_V4:
- case Hexagon::CMPbGTUri_V4:
- case Hexagon::CMPhEQri_V4:
- case Hexagon::CMPhGTUri_V4:
+ case Hexagon::A4_cmpbeqi:
+ case Hexagon::A4_cmpbgtui:
+ case Hexagon::A4_cmpheqi:
+ case Hexagon::A4_cmphgtui:
SrcReg2 = 0;
Value = MI->getOperand(2).getImm();
return true;
}
bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
- // Constant extenders are allowed only for V4 and above.
- if (!Subtarget.hasV4TOps())
- return false;
-
const MCInstrDesc &MID = MI->getDesc();
const uint64_t F = MID.TSFlags;
if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
return (isUInt<6>(MI->getOperand(1).getImm()) &&
isInt<6>(MI->getOperand(2).getImm()));
- case Hexagon::ADD_ri:
+ case Hexagon::A2_addi:
return isInt<8>(MI->getOperand(2).getImm());
case Hexagon::A2_aslh:
case Hexagon::A2_sxth:
case Hexagon::A2_zxtb:
case Hexagon::A2_zxth:
- return Subtarget.hasV4TOps();
+ return true;
}
return true;
return Hexagon::C2_ccombinewt;
// Dealloc_return.
- case Hexagon::DEALLOC_RET_cPt_V4:
- return Hexagon::DEALLOC_RET_cNotPt_V4;
- case Hexagon::DEALLOC_RET_cNotPt_V4:
- return Hexagon::DEALLOC_RET_cPt_V4;
+ case Hexagon::L4_return_t:
+ return Hexagon::L4_return_f;
+ case Hexagon::L4_return_f:
+ return Hexagon::L4_return_t;
}
}
return !invertPredicate ? Hexagon::C2_ccombinewt :
Hexagon::C2_ccombinewf;
- // Word.
- case Hexagon::STriw_f:
- return !invertPredicate ? Hexagon::S2_pstorerit_io:
- Hexagon::S2_pstorerif_io;
- case Hexagon::STriw_indexed_f:
- return !invertPredicate ? Hexagon::S2_pstorerit_io:
- Hexagon::S2_pstorerif_io;
-
// DEALLOC_RETURN.
- case Hexagon::DEALLOC_RET_V4:
- return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
- Hexagon::DEALLOC_RET_cNotPt_V4;
+ case Hexagon::L4_return:
+ return !invertPredicate ? Hexagon::L4_return_t:
+ Hexagon::L4_return_f;
}
llvm_unreachable("Unexpected predicable instruction");
}
// Returns true, if a ST insn can be promoted to a new-value store.
bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
- const HexagonRegisterInfo& QRI = getRegisterInfo();
const uint64_t F = MI->getDesc().TSFlags;
return ((F >> HexagonII::mayNVStorePos) &
- HexagonII::mayNVStoreMask &
- QRI.Subtarget.hasV4TOps());
+ HexagonII::mayNVStoreMask);
}
bool
bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: return false;
- case Hexagon::DEALLOC_RET_V4 :
- case Hexagon::DEALLOC_RET_cPt_V4 :
- case Hexagon::DEALLOC_RET_cNotPt_V4 :
- case Hexagon::DEALLOC_RET_cdnPnt_V4 :
- case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
- case Hexagon::DEALLOC_RET_cdnPt_V4 :
- case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
+ case Hexagon::L4_return:
+ case Hexagon::L4_return_t:
+ case Hexagon::L4_return_f:
+ case Hexagon::L4_return_tnew_pnt:
+ case Hexagon::L4_return_fnew_pnt:
+ case Hexagon::L4_return_tnew_pt:
+ case Hexagon::L4_return_fnew_pt:
return true;
}
}
switch(Opcode) {
case Hexagon::L2_loadri_io:
- case Hexagon::LDriw_f:
case Hexagon::S2_storeri_io:
- case Hexagon::STriw_f:
return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
(Offset <= Hexagon_MEMW_OFFSET_MAX);
case Hexagon::L2_loadrd_io:
- case Hexagon::LDrid_f:
case Hexagon::S2_storerd_io:
- case Hexagon::STrid_f:
return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
(Offset <= Hexagon_MEMD_OFFSET_MAX);
return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
(Offset <= Hexagon_MEMB_OFFSET_MAX);
- case Hexagon::ADD_ri:
+ case Hexagon::A2_addi:
case Hexagon::TFR_FI:
return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
(Offset <= Hexagon_ADDI_OFFSET_MAX);
- case Hexagon::MemOPw_ADDi_V4 :
- case Hexagon::MemOPw_SUBi_V4 :
- case Hexagon::MemOPw_ADDr_V4 :
- case Hexagon::MemOPw_SUBr_V4 :
- case Hexagon::MemOPw_ANDr_V4 :
- case Hexagon::MemOPw_ORr_V4 :
+ case Hexagon::L4_iadd_memopw_io:
+ case Hexagon::L4_isub_memopw_io:
+ case Hexagon::L4_add_memopw_io:
+ case Hexagon::L4_sub_memopw_io:
+ case Hexagon::L4_and_memopw_io:
+ case Hexagon::L4_or_memopw_io:
return (0 <= Offset && Offset <= 255);
- case Hexagon::MemOPh_ADDi_V4 :
- case Hexagon::MemOPh_SUBi_V4 :
- case Hexagon::MemOPh_ADDr_V4 :
- case Hexagon::MemOPh_SUBr_V4 :
- case Hexagon::MemOPh_ANDr_V4 :
- case Hexagon::MemOPh_ORr_V4 :
+ case Hexagon::L4_iadd_memoph_io:
+ case Hexagon::L4_isub_memoph_io:
+ case Hexagon::L4_add_memoph_io:
+ case Hexagon::L4_sub_memoph_io:
+ case Hexagon::L4_and_memoph_io:
+ case Hexagon::L4_or_memoph_io:
return (0 <= Offset && Offset <= 127);
- case Hexagon::MemOPb_ADDi_V4 :
- case Hexagon::MemOPb_SUBi_V4 :
- case Hexagon::MemOPb_ADDr_V4 :
- case Hexagon::MemOPb_SUBr_V4 :
- case Hexagon::MemOPb_ANDr_V4 :
- case Hexagon::MemOPb_ORr_V4 :
+ case Hexagon::L4_iadd_memopb_io:
+ case Hexagon::L4_isub_memopb_io:
+ case Hexagon::L4_add_memopb_io:
+ case Hexagon::L4_sub_memopb_io:
+ case Hexagon::L4_and_memopb_io:
+ case Hexagon::L4_or_memopb_io:
return (0 <= Offset && Offset <= 63);
// LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
switch (MI->getOpcode())
{
- default: return false;
- case Hexagon::MemOPw_ADDi_V4 :
- case Hexagon::MemOPw_SUBi_V4 :
- case Hexagon::MemOPw_ADDr_V4 :
- case Hexagon::MemOPw_SUBr_V4 :
- case Hexagon::MemOPw_ANDr_V4 :
- case Hexagon::MemOPw_ORr_V4 :
- case Hexagon::MemOPh_ADDi_V4 :
- case Hexagon::MemOPh_SUBi_V4 :
- case Hexagon::MemOPh_ADDr_V4 :
- case Hexagon::MemOPh_SUBr_V4 :
- case Hexagon::MemOPh_ANDr_V4 :
- case Hexagon::MemOPh_ORr_V4 :
- case Hexagon::MemOPb_ADDi_V4 :
- case Hexagon::MemOPb_SUBi_V4 :
- case Hexagon::MemOPb_ADDr_V4 :
- case Hexagon::MemOPb_SUBr_V4 :
- case Hexagon::MemOPb_ANDr_V4 :
- case Hexagon::MemOPb_ORr_V4 :
- case Hexagon::MemOPb_SETBITi_V4:
- case Hexagon::MemOPh_SETBITi_V4:
- case Hexagon::MemOPw_SETBITi_V4:
- case Hexagon::MemOPb_CLRBITi_V4:
- case Hexagon::MemOPh_CLRBITi_V4:
- case Hexagon::MemOPw_CLRBITi_V4:
+ default: return false;
+ case Hexagon::L4_iadd_memopw_io:
+ case Hexagon::L4_isub_memopw_io:
+ case Hexagon::L4_add_memopw_io:
+ case Hexagon::L4_sub_memopw_io:
+ case Hexagon::L4_and_memopw_io:
+ case Hexagon::L4_or_memopw_io:
+ case Hexagon::L4_iadd_memoph_io:
+ case Hexagon::L4_isub_memoph_io:
+ case Hexagon::L4_add_memoph_io:
+ case Hexagon::L4_sub_memoph_io:
+ case Hexagon::L4_and_memoph_io:
+ case Hexagon::L4_or_memoph_io:
+ case Hexagon::L4_iadd_memopb_io:
+ case Hexagon::L4_isub_memopb_io:
+ case Hexagon::L4_add_memopb_io:
+ case Hexagon::L4_sub_memopb_io:
+ case Hexagon::L4_and_memopb_io:
+ case Hexagon::L4_or_memopb_io:
+ case Hexagon::L4_ior_memopb_io:
+ case Hexagon::L4_ior_memoph_io:
+ case Hexagon::L4_ior_memopw_io:
+ case Hexagon::L4_iand_memopb_io:
+ case Hexagon::L4_iand_memoph_io:
+ case Hexagon::L4_iand_memopw_io:
return true;
}
return false;
case Hexagon::A4_pzxthfnew:
case Hexagon::A4_pzxtht:
case Hexagon::A4_pzxthtnew:
- case Hexagon::ADD_ri_cPt:
- case Hexagon::ADD_ri_cNotPt:
+ case Hexagon::A2_paddit:
+ case Hexagon::A2_paddif:
case Hexagon::C2_ccombinewt:
case Hexagon::C2_ccombinewf:
return true;
bool HexagonInstrInfo::
isConditionalLoad (const MachineInstr* MI) const {
- const HexagonRegisterInfo& QRI = getRegisterInfo();
switch (MI->getOpcode())
{
default: return false;
case Hexagon::L2_ploadruhf_io:
case Hexagon::L2_ploadrubt_io:
case Hexagon::L2_ploadrubf_io:
- return true;
case Hexagon::L2_ploadrdt_pi:
case Hexagon::L2_ploadrdf_pi:
case Hexagon::L2_ploadrit_pi:
case Hexagon::L2_ploadruhf_pi:
case Hexagon::L2_ploadrubt_pi:
case Hexagon::L2_ploadrubf_pi:
- return QRI.Subtarget.hasV4TOps();
case Hexagon::L4_ploadrdt_rr:
case Hexagon::L4_ploadrdf_rr:
case Hexagon::L4_ploadrbt_rr:
case Hexagon::L4_ploadruhf_rr:
case Hexagon::L4_ploadrit_rr:
case Hexagon::L4_ploadrif_rr:
- return QRI.Subtarget.hasV4TOps();
+ return true;
}
}
// is not valid for new-value stores.
bool HexagonInstrInfo::
isConditionalStore (const MachineInstr* MI) const {
- const HexagonRegisterInfo& QRI = getRegisterInfo();
switch (MI->getOpcode())
{
default: return false;
case Hexagon::S4_pstorerif_rr:
case Hexagon::S2_pstorerit_pi:
case Hexagon::S2_pstorerif_pi:
- return QRI.Subtarget.hasV4TOps();
// V4 global address store before promoting to dot new.
- case Hexagon::STd_GP_cPt_V4 :
- case Hexagon::STd_GP_cNotPt_V4 :
- case Hexagon::STb_GP_cPt_V4 :
- case Hexagon::STb_GP_cNotPt_V4 :
- case Hexagon::STh_GP_cPt_V4 :
- case Hexagon::STh_GP_cNotPt_V4 :
- case Hexagon::STw_GP_cPt_V4 :
- case Hexagon::STw_GP_cNotPt_V4 :
- return QRI.Subtarget.hasV4TOps();
+ case Hexagon::S4_pstorerdt_abs:
+ case Hexagon::S4_pstorerdf_abs:
+ case Hexagon::S4_pstorerbt_abs:
+ case Hexagon::S4_pstorerbf_abs:
+ case Hexagon::S4_pstorerht_abs:
+ case Hexagon::S4_pstorerhf_abs:
+ case Hexagon::S4_pstorerit_abs:
+ case Hexagon::S4_pstorerif_abs:
+ return true;
// Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
// from the "Conditional Store" list. Because a predicated new value store
switch (MI->getOpcode()) {
default: llvm_unreachable("Unknown .new type");
// store new value byte
- case Hexagon::STrib_shl_V4:
- return Hexagon::STrib_shl_nv_V4;
-
- case Hexagon::STrih_shl_V4:
- return Hexagon::STrih_shl_nv_V4;
+ case Hexagon::S4_storerb_ur:
+ return Hexagon::S4_storerbnew_ur;
- case Hexagon::STriw_f:
- return Hexagon::S2_storerinew_io;
+ case Hexagon::S4_storerh_ur:
+ return Hexagon::S4_storerhnew_ur;
- case Hexagon::STriw_indexed_f:
- return Hexagon::S4_storerinew_rr;
-
- case Hexagon::STriw_shl_V4:
- return Hexagon::STriw_shl_nv_V4;
+ case Hexagon::S4_storeri_ur:
+ return Hexagon::S4_storerinew_ur;
}
return 0;
}
bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
-
- // Constant extenders are allowed only for V4 and above.
- if (!Subtarget.hasV4TOps())
- return false;
-
const uint64_t F = MI->getDesc().TSFlags;
unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
if (isExtended) // Instruction must be extended.
// Returns true if a particular operand is extendable for an instruction.
bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
unsigned short OperandNum) const {
- // Constant extenders are allowed only for V4 and above.
- if (!Subtarget.hasV4TOps())
- return false;
-
const uint64_t F = MI->getDesc().TSFlags;
return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
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