Added multiclass for post-increment load instructions.

[oota-llvm.git] / lib / Target / Hexagon / HexagonInstrFormats.td

diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td
index a64c7a18164f09dbbd804b185a09df3cc169c758..71c620b13177d42a6692317f07386bf3281f6627 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -27,6 +27,34 @@ def TypeSYSTEM : Type<7>;
 def TypeXTYPE  : Type<8>;
 def TypeMARKER : Type<31>;
 
+// Maintain list of valid subtargets for each instruction.
+class SubTarget<bits<4> value> {
+  bits<4> Value = value;
+}
+
+def HasV2SubT     : SubTarget<0xf>;
+def HasV2SubTOnly : SubTarget<0x1>;
+def NoV2SubT      : SubTarget<0x0>;
+def HasV3SubT     : SubTarget<0xe>;
+def HasV3SubTOnly : SubTarget<0x2>;
+def NoV3SubT      : SubTarget<0x1>;
+def HasV4SubT     : SubTarget<0xc>;
+def NoV4SubT      : SubTarget<0x3>;
+def HasV5SubT     : SubTarget<0x8>;
+def NoV5SubT      : SubTarget<0x7>;
+
+// Addressing modes for load/store instructions
+class AddrModeType<bits<4> value> {
+  bits<4> Value = value;
+}
+
+def NoAddrMode     : AddrModeType<0>;  // No addressing mode
+def Absolute       : AddrModeType<1>;  // Absolute addressing mode
+def AbsoluteSet    : AddrModeType<2>;  // Absolute set addressing mode
+def BaseImmOffset  : AddrModeType<3>;  // Indirect with offset
+def BaseLongOffset : AddrModeType<4>;  // Indirect with long offset
+def BaseRegOffset  : AddrModeType<5>;  // Indirect with register offset
+
 //===----------------------------------------------------------------------===//
 //                         Intruction Class Declaration +
 //===----------------------------------------------------------------------===//
@@ -55,10 +83,38 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   // Predicated instructions.
   bits<1> isPredicated = 0;
   let TSFlags{6} = isPredicated;
+  bits<1> isPredicatedNew = 0;
+  let TSFlags{7} = isPredicatedNew;
+
+  // Stores that can be newified.
+  bits<1> isNVStorable = 0;
+  let TSFlags{8} = isNVStorable;
 
-  // Dot new value store instructions.
+  // New-value store instructions.
   bits<1> isNVStore = 0;
-  let TSFlags{8} = isNVStore;
+  let TSFlags{9} = isNVStore;
+
+  // Immediate extender helper fields.
+  bits<1> isExtendable = 0;
+  let TSFlags{10} = isExtendable; // Insn may be extended.
+  bits<1> isExtended = 0;
+  let TSFlags{11} = isExtended; // Insn must be extended.
+  bits<3> opExtendable = 0;
+  let TSFlags{14-12} = opExtendable; // Which operand may be extended.
+  bits<1> isExtentSigned = 0;
+  let TSFlags{15} = isExtentSigned; // Signed or unsigned range.
+  bits<5> opExtentBits = 0;
+  let TSFlags{20-16} = opExtentBits; //Number of bits of range before extending.
+
+  // If an instruction is valid on a subtarget (v2-v5), set the corresponding
+  // bit from validSubTargets. v2 is the least significant bit.
+  // By default, instruction is valid on all subtargets.
+  SubTarget validSubTargets = HasV2SubT;
+  let TSFlags{24-21} = validSubTargets.Value;
+
+  // Addressing mode for load/store instrutions.
+  AddrModeType addrMode = NoAddrMode;
+  let TSFlags{28-25} = addrMode.Value;
 
   // Fields used for relation models.
   string BaseOpcode = "";
@@ -66,7 +122,10 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   string PredSense = "";
   string PNewValue = "";
   string InputType = "";    // Input is "imm" or "reg" type.
-  // *** The code above must match HexagonBaseInfo.h ***
+  string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
+  string isFloat = "false"; // Set to "true" for the floating-point load/store.
+
+  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 }
 
 //===----------------------------------------------------------------------===//