switch (VA.getLocInfo()) {
default:
// Loc info must be one of Full, SExt, ZExt, or AExt.
- assert(0 && "Unknown loc info!");
+ llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
break;
case CCValAssign::SExt:
SDValue
HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
- default: assert(0 && "Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
// Frame & Return address. Currently unimplemented.
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GlobalTLSAddress:
- assert(0 && "TLS not implemented for Hexagon.");
+ llvm_unreachable("TLS not implemented for Hexagon.");
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
FuncInfo->addAllocaAdjustInst(MI);
return BB;
}
- default:
- assert(false && "Unexpected instr type to insert");
+ default: llvm_unreachable("Unexpected instr type to insert");
} // switch
- return NULL;
}
//===----------------------------------------------------------------------===//
case 'r': // R0-R31
switch (VT.getSimpleVT().SimpleTy) {
default:
- assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
+ llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::i32:
case MVT::i16:
case MVT::i8:
return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
}
default:
- assert(0 && "Unknown asm register class");
+ llvm_unreachable("Unknown asm register class");
}
}