Change TargetInstrInfo::isMoveInstr to return source and destination sub-register...

[oota-llvm.git] / lib / Target / CellSPU / SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index d88b2e9e82fa708dd17a3c93edfb55d006eb87e8..5802eb68feec7637782b721fb843b36531bf501c 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -64,7 +64,10 @@ SPUInstrInfo::getPointerRegClass() const
 bool
 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
                           unsigned& sourceReg,
-                          unsigned& destReg) const {
+                          unsigned& destReg,
+                          unsigned& SrcSR, unsigned& DstSR) const {
+  SrcSR = DstSR = 0;  // No sub-registers.
+
   // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
   // cases where we can safely say that what's being done is really a move
   // (see how PowerPC does this -- it's the model for this code too.)
@@ -130,7 +133,32 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
   case SPU::ORi32_v4i32:
   case SPU::ORi64_v2i64:
   case SPU::ORf32_v4f32:
-  case SPU::ORf64_v2f64: {
+  case SPU::ORf64_v2f64:
+  case SPU::ORi128_r64:
+  case SPU::ORi128_f64:
+  case SPU::ORi128_r32:
+  case SPU::ORi128_f32:
+  case SPU::ORi128_r16:
+  case SPU::ORi128_r8:
+  case SPU::ORi128_vec:
+  case SPU::ORr64_i128:
+  case SPU::ORf64_i128:
+  case SPU::ORr32_i128:
+  case SPU::ORf32_i128:
+  case SPU::ORr16_i128:
+  case SPU::ORr8_i128:
+  case SPU::ORvec_i128:
+  case SPU::ORr16_r32:
+  case SPU::ORr8_r32:
+  case SPU::ORr32_r16:
+  case SPU::ORr32_r8:
+  case SPU::ORr32_r64:
+  case SPU::ORr16_r64:
+  case SPU::ORr8_r64:
+  case SPU::ORr64_r32:
+  case SPU::ORr64_r16:
+  case SPU::ORr64_r8:
+  {
     assert(MI.getNumOperands() == 2 &&
            MI.getOperand(0).isReg() &&
            MI.getOperand(1).isReg() &&
@@ -653,7 +681,7 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
 
   unsigned Opc = unsigned(Cond[0].getImm());
   // Pretty dull mapping between the two conditions that SPU can generate:
-  for (int i = sizeof(revconds)/sizeof(revconds[0]); i >= 0; --i) {
+  for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
     if (revconds[i].Opc == Opc) {
       Cond[0].setImm(revconds[i].RevCondOpc);
       return false;