#include "SPUGenInstrInfo.inc"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/Streams.h"
+#include "llvm/Support/Debug.h"
using namespace llvm;
|| opc == SPU::BI);
}
+ //! Predicate for a conditional branch instruction
inline bool isCondBranch(const MachineInstr *I) {
unsigned opc = I->getOpcode();
: TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
TM(tm),
RI(*TM.getSubtargetImpl(), *this)
-{
- /* NOP */
-}
+{ /* NOP */ }
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
bool
SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
- unsigned& destReg) const {
+ unsigned& destReg,
+ unsigned& SrcSR, unsigned& DstSR) const {
+ SrcSR = DstSR = 0; // No sub-registers.
+
// Primarily, ORI and OR are generated by copyRegToReg. But, there are other
// cases where we can safely say that what's being done is really a move
// (see how PowerPC does this -- it's the model for this code too.)
case SPU::ORIi8i32:
case SPU::AHIvec:
case SPU::AHIr16:
- case SPU::AIvec:
+ case SPU::AIv4i32:
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
assert(MI.getNumOperands() == 3 &&
"wrong number of operands to AIr32");
if (MI.getOperand(0).isReg() &&
- (MI.getOperand(1).isReg() ||
- MI.getOperand(1).isFI()) &&
+ MI.getOperand(1).isReg() &&
(MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0)) {
sourceReg = MI.getOperand(1).getReg();
case SPU::ORi32_v4i32:
case SPU::ORi64_v2i64:
case SPU::ORf32_v4f32:
- case SPU::ORf64_v2f64: {
+ case SPU::ORf64_v2f64:
+ case SPU::ORi128_r64:
+ case SPU::ORi128_f64:
+ case SPU::ORi128_r32:
+ case SPU::ORi128_f32:
+ case SPU::ORi128_r16:
+ case SPU::ORi128_r8:
+ case SPU::ORi128_vec:
+ case SPU::ORr64_i128:
+ case SPU::ORf64_i128:
+ case SPU::ORr32_i128:
+ case SPU::ORf32_i128:
+ case SPU::ORr16_i128:
+ case SPU::ORr8_i128:
+ case SPU::ORvec_i128:
+ case SPU::ORr16_r32:
+ case SPU::ORr8_r32:
+ case SPU::ORr32_r16:
+ case SPU::ORr32_r8:
+ case SPU::ORr32_r64:
+ case SPU::ORr16_r64:
+ case SPU::ORr8_r64:
+ case SPU::ORr64_r32:
+ case SPU::ORr64_r16:
+ case SPU::ORr64_r8:
+ {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
- "invalid SPU OR<type>_<vec> instruction!");
+ "invalid SPU OR<type>_<vec> or LR instruction!");
if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
sourceReg = MI.getOperand(0).getReg();
destReg = MI.getOperand(0).getReg();
case SPU::ORv16i8:
case SPU::ORv8i16:
case SPU::ORv4i32:
+ case SPU::ORv2i64:
+ case SPU::ORr8:
+ case SPU::ORr16:
case SPU::ORr32:
case SPU::ORr64:
case SPU::ORf32:
case SPU::LQDr16: {
const MachineOperand MOp1 = MI->getOperand(1);
const MachineOperand MOp2 = MI->getOperand(2);
- if (MOp1.isImm()
- && (MOp2.isFI()
- || (MOp2.isReg() && MOp2.getReg() == SPU::R1))) {
- if (MOp2.isFI())
- FrameIndex = MOp2.getIndex();
- else
- FrameIndex = MOp1.getImm() / SPUFrameInfo::stackSlotSize();
+ if (MOp1.isImm() && MOp2.isFI()) {
+ FrameIndex = MOp2.getIndex();
return MI->getOperand(0).getReg();
}
break;
}
- case SPU::LQXv4i32:
- case SPU::LQXr128:
- case SPU::LQXr64:
- case SPU::LQXr32:
- case SPU::LQXr16:
- if (MI->getOperand(1).isReg() && MI->getOperand(2).isReg()
- && (MI->getOperand(2).getReg() == SPU::R1
- || MI->getOperand(1).getReg() == SPU::R1)) {
- FrameIndex = MI->getOperand(2).getIndex();
- return MI->getOperand(0).getReg();
- }
- break;
}
return 0;
}
}
break;
}
-#if 0
- case SPU::STQXv16i8:
- case SPU::STQXv8i16:
- case SPU::STQXv4i32:
- case SPU::STQXv4f32:
- case SPU::STQXv2f64:
- case SPU::STQXr128:
- case SPU::STQXr64:
- case SPU::STQXr32:
- case SPU::STQXr16:
- case SPU::STQXr8:
- if (MI->getOperand(1).isReg() && MI->getOperand(2).isReg()
- && (MI->getOperand(2).getReg() == SPU::R1
- || MI->getOperand(1).getReg() == SPU::R1)) {
- FrameIndex = MI->getOperand(2).getIndex();
- return MI->getOperand(0).getReg();
- }
- break;
-#endif
}
return 0;
}
// reg class to any other reg class containing R3. This is required because
// we instruction select bitconvert i64 -> f64 as a noop for example, so our
// types have no specific meaning.
-
+
if (DestRC == SPU::R8CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R16CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R32CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R32FPRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R64CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R64FPRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
- .addReg(SrcReg);
- } /* else if (DestRC == SPU::GPRCRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
- .addReg(SrcReg);
- } */ else if (DestRC == SPU::VECREGRegisterClass) {
- BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
- .addReg(SrcReg);
+ BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg);
+ } else if (DestRC == SPU::GPRCRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg);
+ } else if (DestRC == SPU::VECREGRegisterClass) {
+ BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
} else {
// Attempt to copy unknown/unsupported register class!
return false;
}
-
+
return true;
}
}
}
+//! Return true if the specified load or store can be folded
+bool
+SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
+ const SmallVectorImpl<unsigned> &Ops) const {
+ if (Ops.size() != 1) return false;
+
+ // Make sure this is a reg-reg copy.
+ unsigned Opc = MI->getOpcode();
+
+ switch (Opc) {
+ case SPU::ORv16i8:
+ case SPU::ORv8i16:
+ case SPU::ORv4i32:
+ case SPU::ORv2i64:
+ case SPU::ORr8:
+ case SPU::ORr16:
+ case SPU::ORr32:
+ case SPU::ORr64:
+ case SPU::ORf32:
+ case SPU::ORf64:
+ if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
+ return true;
+ break;
+ }
+
+ return false;
+}
+
/// foldMemoryOperand - SPU, like PPC, can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *
const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const
{
-#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
- if (Ops.size() != 1) return NULL;
+ if (Ops.size() != 1) return 0;
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
MachineInstr *NewMI = 0;
-
- if ((Opc == SPU::ORr32
- || Opc == SPU::ORv4i32)
- && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
+
+ switch (Opc) {
+ case SPU::ORv16i8:
+ case SPU::ORv8i16:
+ case SPU::ORv4i32:
+ case SPU::ORv2i64:
+ case SPU::ORr8:
+ case SPU::ORr16:
+ case SPU::ORr32:
+ case SPU::ORr64:
+ case SPU::ORf32:
+ case SPU::ORf64:
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
- NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32))
- .addReg(InReg, false, false, isKill),
- FrameIndex);
+ MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32));
+
+ MIB.addReg(InReg, false, false, isKill);
+ NewMI = addFrameReference(MIB, FrameIndex);
}
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
+ MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
+
+ MIB.addReg(OutReg, true, false, false, isDead);
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
? SPU::STQDr32 : SPU::STQXr32;
- NewMI = addFrameReference(BuildMI(MF, TII.get(Opc))
- .addReg(OutReg, true, false, false, isDead), FrameIndex);
- }
+ NewMI = addFrameReference(MIB, FrameIndex);
+ break;
+ }
}
return NewMI;
-#else
- return 0;
-#endif
}
//! Branch analysis
-/*
+/*!
\note This code was kiped from PPC. There may be more branch analysis for
CellSPU than what's currently done here.
*/
// Get the last instruction in the block.
MachineInstr *LastInst = I;
-
+
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (isUncondBranch(LastInst)) {
} else if (isCondBranch(LastInst)) {
// Block ends with fall-through condbranch.
TBB = LastInst->getOperand(1).getMBB();
+ DEBUG(cerr << "Pushing LastInst: ");
+ DEBUG(LastInst->dump());
+ Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
Cond.push_back(LastInst->getOperand(0));
- Cond.push_back(LastInst->getOperand(1));
return false;
}
// Otherwise, don't know what this is.
return true;
}
-
+
// Get the instruction before it if it's a terminator.
MachineInstr *SecondLastInst = I;
if (SecondLastInst && I != MBB.begin() &&
isUnpredicatedTerminator(--I))
return true;
-
+
// If the block ends with a conditional and unconditional branch, handle it.
if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
TBB = SecondLastInst->getOperand(1).getMBB();
+ DEBUG(cerr << "Pushing SecondLastInst: ");
+ DEBUG(SecondLastInst->dump());
+ Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
Cond.push_back(SecondLastInst->getOperand(0));
- Cond.push_back(SecondLastInst->getOperand(1));
FBB = LastInst->getOperand(0).getMBB();
return false;
}
-
+
// If the block ends with two unconditional branches, handle it. The second
// one is not executed, so remove it.
if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
// Otherwise, can't handle this.
return true;
}
-
+
unsigned
SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator I = MBB.end();
return 0;
// Remove the first branch.
+ DEBUG(cerr << "Removing branch: ");
+ DEBUG(I->dump());
I->eraseFromParent();
I = MBB.end();
if (I == MBB.begin())
return 1;
--I;
- if (isCondBranch(I))
+ if (!(isCondBranch(I) || isUncondBranch(I)))
return 1;
// Remove the second branch.
+ DEBUG(cerr << "Removing second branch: ");
+ DEBUG(I->dump());
I->eraseFromParent();
return 2;
}
-
+
unsigned
SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
- assert((Cond.size() == 2 || Cond.size() == 0) &&
+ assert((Cond.size() == 2 || Cond.size() == 0) &&
"SPU branch conditions have two components!");
-
+
// One-way branch.
if (FBB == 0) {
- if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, get(SPU::BR)).addMBB(TBB);
- else { // Conditional branch
- /* BuildMI(&MBB, get(SPU::BRNZ))
- .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); */
- cerr << "SPUInstrInfo::InsertBranch conditional branch logic needed\n";
- abort();
+ if (Cond.empty()) {
+ // Unconditional branch
+ MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
+ MIB.addMBB(TBB);
+
+ DEBUG(cerr << "Inserted one-way uncond branch: ");
+ DEBUG((*MIB).dump());
+ } else {
+ // Conditional branch
+ MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
+ MIB.addReg(Cond[1].getReg()).addMBB(TBB);
+
+ DEBUG(cerr << "Inserted one-way cond branch: ");
+ DEBUG((*MIB).dump());
}
return 1;
+ } else {
+ MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
+ MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
+
+ // Two-way Conditional Branch.
+ MIB.addReg(Cond[1].getReg()).addMBB(TBB);
+ MIB2.addMBB(FBB);
+
+ DEBUG(cerr << "Inserted conditional branch: ");
+ DEBUG((*MIB).dump());
+ DEBUG(cerr << "part 2: ");
+ DEBUG((*MIB2).dump());
+ return 2;
}
-
- // Two-way Conditional Branch.
-#if 0
- BuildMI(&MBB, get(SPU::BRNZ))
- .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, get(SPU::BR)).addMBB(FBB);
-#else
- cerr << "SPUInstrInfo::InsertBranch conditional branch logic needed\n";
- abort();
-#endif
-
- return 2;
}
+bool
+SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
+ return (!MBB.empty() && isUncondBranch(&MBB.back()));
+}
+//! Reverses a branch's condition, returning false on success.
+bool
+SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
+ const {
+ // Pretty brainless way of inverting the condition, but it works, considering
+ // there are only two conditions...
+ static struct {
+ unsigned Opc; //! The incoming opcode
+ unsigned RevCondOpc; //! The reversed condition opcode
+ } revconds[] = {
+ { SPU::BRNZr32, SPU::BRZr32 },
+ { SPU::BRNZv4i32, SPU::BRZv4i32 },
+ { SPU::BRZr32, SPU::BRNZr32 },
+ { SPU::BRZv4i32, SPU::BRNZv4i32 },
+ { SPU::BRHNZr16, SPU::BRHZr16 },
+ { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
+ { SPU::BRHZr16, SPU::BRHNZr16 },
+ { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
+ };
+
+ unsigned Opc = unsigned(Cond[0].getImm());
+ // Pretty dull mapping between the two conditions that SPU can generate:
+ for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
+ if (revconds[i].Opc == Opc) {
+ Cond[0].setImm(revconds[i].RevCondOpc);
+ return false;
+ }
+ }
+ return true;
+}
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