Add new shorter predicates for testing machine operands for various types:

[oota-llvm.git] / lib / Target / CellSPU / SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index ea7e107c490ec3264121d110218536fbd9e93f3f..1b321b6eb173490a2f1178e29acd2af03b725858 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -1,10 +1,9 @@
-//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ------*- C++ -*-===//
+//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by a team from the Computer Systems Research
-// Department at The Aerospace Corporation and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -49,50 +48,48 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
     break;
   case SPU::ORIv4i32:
   case SPU::ORIr32:
-  case SPU::ORIf64:
-  case SPU::ORIf32:
   case SPU::ORIr64:
   case SPU::ORHIv8i16:
   case SPU::ORHIr16:
-    // case SPU::ORHI1To2:
+  case SPU::ORHI1To2:
   case SPU::ORBIv16i8:
-    //case SPU::ORBIr8:
+  case SPU::ORBIr8:
   case SPU::ORI2To4:
-    // case SPU::ORI1To4:
+  case SPU::ORI1To4:
   case SPU::AHIvec:
   case SPU::AHIr16:
   case SPU::AIvec:
-  case SPU::AIr32:
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            MI.getOperand(2).isImmediate() &&
            "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
-    if (MI.getOperand(2).getImmedValue() == 0) {
+    if (MI.getOperand(2).getImm() == 0) {
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+    }
+    break;
+  case SPU::AIr32:
+    assert(MI.getNumOperands() == 3 &&
+           "wrong number of operands to AIr32");
+    if (MI.getOperand(0).isRegister() &&
+        (MI.getOperand(1).isRegister() ||
+         MI.getOperand(1).isFrameIndex()) &&
+        (MI.getOperand(2).isImmediate() &&
+         MI.getOperand(2).getImm() == 0)) {
       sourceReg = MI.getOperand(1).getReg();
       destReg = MI.getOperand(0).getReg();
       return true;
     }
     break;
-#if 0
-  case SPU::ORIf64:
-  case SPU::ORIf32:
-    // Special case because there's no third immediate operand to the
-    // instruction (the constant is embedded in the instruction)
-    assert(MI.getOperand(0).isRegister() &&
-          MI.getOperand(1).isRegister() &&
-          "ORIf32/f64: operands not registers");
-    sourceReg = MI.getOperand(1).getReg();
-    destReg = MI.getOperand(0).getReg();
-    return true;
-#endif
-    // case SPU::ORv16i8_i8:
+  case SPU::ORv16i8_i8:
   case SPU::ORv8i16_i16:
   case SPU::ORv4i32_i32:
   case SPU::ORv2i64_i64:
   case SPU::ORv4f32_f32:
   case SPU::ORv2f64_f64:
-    // case SPU::ORi8_v16i8:
+  case SPU::ORi8_v16i8:
   case SPU::ORi16_v8i16:
   case SPU::ORi32_v4i32:
   case SPU::ORi64_v2i64:
@@ -103,6 +100,8 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
   case SPU::ORv4i32:
   case SPU::ORr32:
   case SPU::ORr64:
+  case SPU::ORf32:
+  case SPU::ORf64:
   case SPU::ORgprc:
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
@@ -138,9 +137,9 @@ SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
   case SPU::LQXr64:
   case SPU::LQXr32:
   case SPU::LQXr16:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
         MI->getOperand(2).isFrameIndex()) {
-      FrameIndex = MI->getOperand(2).getFrameIndex();
+      FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
     }
     break;
@@ -172,9 +171,9 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
   case SPU::STQXr32:
   case SPU::STQXr16:
     // case SPU::STQXr8:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
         MI->getOperand(2).isFrameIndex()) {
-      FrameIndex = MI->getOperand(2).getFrameIndex();
+      FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
     }
     break;