| I-- | * | | * | * | |
| I++M | * | | | | |
+* Workarounds and features
+Blackfin CPUs have bugs. Each model comes in a number of silicon revisions with
+different bugs. We learn about the CPU model from the -mcpu switch.
+
+** Interpretation of -mcpu value
+- -mcpu=bf527 refers to the latest known BF527 revision
+- -mcpu=bf527-0.2 refers to silicon rev. 0.2
+- -mcpu=bf527-any refers to all known revisions
+- -mcpu=bf527-none disables all workarounds
+
+The -mcpu setting affects the __SILICON_REVISION__ macro and enabled workarounds:
+
+| -mcpu | __SILICON_REVISION__ | Workarounds |
+|------------+----------------------+--------------------|
+| bf527 | Def Latest | Specific to latest |
+| bf527-1.3 | Def 0x0103 | Specific to 1.3 |
+| bf527-any | Def 0xffff | All bf527-x.y |
+| bf527-none | Undefined | None |
+
+These are the known cores and revisions:
+
+| Core | Silicon | Processors |
+|-------------+--------------------+-------------------------|
+| Edinburgh | 0.3, 0.4, 0.5, 0.6 | BF531 BF532 BF533 |
+| Braemar | 0.2, 0.3 | BF534 BF536 BF537 |
+| Stirling | 0.3, 0.4, 0.5 | BF538 BF539 |
+| Moab | 0.0, 0.1, 0.2 | BF542 BF544 BF548 BF549 |
+| Teton | 0.3, 0.5 | BF561 |
+| Kookaburra | 0.0, 0.1, 0.2 | BF523 BF525 BF527 |
+| Mockingbird | 0.0, 0.1 | BF522 BF524 BF526 |
+| Brodie | 0.0, 0.1 | BF512 BF514 BF516 BF518 |
+
+
+** Compiler implemented workarounds
+Most workarounds are implemented in header files and source code using the
+__ADSPBF527__ macros. A few workarounds require compiler support.
+
+| Anomaly | Macro | GCC Switch |
+|----------+--------------------------------+------------------|
+| Any | __WORKAROUNDS_ENABLED | |
+| 05000074 | WA_05000074 | |
+| 05000244 | __WORKAROUND_SPECULATIVE_SYNCS | -mcsync-anomaly |
+| 05000245 | __WORKAROUND_SPECULATIVE_LOADS | -mspecld-anomaly |
+| 05000257 | WA_05000257 | |
+| 05000283 | WA_05000283 | |
+| 05000312 | WA_LOAD_LCREGS | |
+| 05000315 | WA_05000315 | |
+| 05000371 | __WORKAROUND_RETS | |
+| 05000426 | __WORKAROUND_INDIRECT_CALLS | Not -micplb |
+
+** GCC feature switches
+| Switch | Description |
+|---------------------------+----------------------------------------|
+| -msim | Use simulator runtime |
+| -momit-leaf-frame-pointer | Omit frame pointer for leaf functions |
+| -mlow64k | |
+| -mcsync-anomaly | |
+| -mspecld-anomaly | |
+| -mid-shared-library | |
+| -mleaf-id-shared-library | |
+| -mshared-library-id= | |
+| -msep-data | Enable separate data segment |
+| -mlong-calls | Use indirect calls |
+| -mfast-fp | |
+| -mfdpic | |
+| -minline-plt | |
+| -mstack-check-l1 | Do stack checking in L1 scratch memory |
+| -mmulticore | Enable multicore support |
+| -mcorea | Build for Core A |
+| -mcoreb | Build for Core B |
+| -msdram | Build for SDRAM |
+| -micplb | Assume ICPLBs are enabled at runtime. |
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