Matches MachineInstr changes.

[oota-llvm.git] / lib / Target / Alpha / AlphaRegisterInfo.cpp

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 1b6fa4490839dc3a964ed15832770c1c0f741649..6be5e074a396d4d10bcb765330fc70b666009812 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -51,14 +51,9 @@ static long getLower16(long l)
   return l - h * IMM_MULT;
 }
 
-static int getUID()
-{
-  static int id = 0;
-  return ++id;
-}
-
-AlphaRegisterInfo::AlphaRegisterInfo()
-  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
+AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
+  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
+    TII(tii)
 {
 }
 
@@ -112,21 +107,21 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
    switch(Opc) {
    default:
      break;
-   case Alpha::BIS:
+   case Alpha::BISr:
    case Alpha::CPYSS:
    case Alpha::CPYST:
      if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
        if (OpNum == 0) {  // move -> store
         unsigned InReg = MI->getOperand(1).getReg();
-        Opc = (Opc == Alpha::BIS) ? Alpha::STQ : 
+        Opc = (Opc == Alpha::BISr) ? Alpha::STQ : 
           ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
-        return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
+        return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
           .addReg(Alpha::F31);
        } else {           // load -> move
         unsigned OutReg = MI->getOperand(0).getReg();
-        Opc = (Opc == Alpha::BIS) ? Alpha::LDQ : 
+        Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : 
           ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
-        return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
+        return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
           .addReg(Alpha::F31);
        }
      }
@@ -142,7 +137,7 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                      const TargetRegisterClass *RC) const {
   //  std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
   if (RC == Alpha::GPRCRegisterClass) {
-    BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+    BuildMI(MBB, MI, Alpha::BISr, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == Alpha::F4RCRegisterClass) {
     BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == Alpha::F8RCRegisterClass) {
@@ -211,11 +206,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 
       MachineInstr *New;
       if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
-         New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+        New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
           .addImm(-Amount).addReg(Alpha::R30);
       } else {
          assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
-         New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+         New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
           .addImm(Amount).addReg(Alpha::R30);
       }
 
@@ -272,7 +267,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
     MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
     //insert the new
-    MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
+    MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28)
       .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
     MBB.insert(II, nMI);
   } else {
@@ -347,7 +342,7 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
     BuildMI(MBB, MBBI, Alpha::STQ, 3)
       .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
     //this must be the last instr in the prolog
-    BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15)
+    BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R15)
       .addReg(Alpha::R30).addReg(Alpha::R30);
   }
 
@@ -370,7 +365,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
   if (FP)
   {
     //copy the FP into the SP (discards allocas)
-    BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R30).addReg(Alpha::R15)
+    BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R30).addReg(Alpha::R15)
       .addReg(Alpha::R15);
     //restore the FP
     BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);