-//===- AlphaRegisterInfo.cpp - Alpha Register Information ---*- C++ -*-----===//
-//
+//===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the Alpha implementation of the MRegisterInfo class.
#define DEBUG_TYPE "reginfo"
#include "Alpha.h"
-#include "AlphaInstrBuilder.h"
#include "AlphaRegisterInfo.h"
#include "llvm/Constants.h"
#include "llvm/Type.h"
+#include "llvm/Function.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include <iostream>
using namespace llvm;
+namespace llvm {
+ extern cl::opt<bool> EnableAlphaLSMark;
+}
-AlphaRegisterInfo::AlphaRegisterInfo()
- : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
+//These describe LDAx
+static const int IMM_LOW = -32768;
+static const int IMM_HIGH = 32767;
+static const int IMM_MULT = 65536;
+
+static long getUpper16(long l)
+{
+ long y = l / IMM_MULT;
+ if (l % IMM_MULT > IMM_HIGH)
+ ++y;
+ return y;
+}
+
+static long getLower16(long l)
{
+ long h = getUpper16(l);
+ return l - h * IMM_MULT;
}
-static const TargetRegisterClass *getClass(unsigned SrcReg) {
- if (Alpha::FPRCRegisterClass->contains(SrcReg))
- return Alpha::FPRCRegisterClass;
- assert(Alpha::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
- return Alpha::GPRCRegisterClass;
+static int getUID()
+{
+ static int id = 0;
+ return ++id;
}
-void
+AlphaRegisterInfo::AlphaRegisterInfo()
+ : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
+{
+}
+
+void
AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- unsigned SrcReg, int FrameIdx) const {
+ unsigned SrcReg, int FrameIdx,
+ const TargetRegisterClass *RC) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
- BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addImm(FrameIdx * 8).addReg(Alpha::R30);
- // assert(0 && "TODO");
+ if (EnableAlphaLSMark)
+ BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
+ .addImm(getUID());
+ if (RC == Alpha::F4RCRegisterClass)
+ BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::F8RCRegisterClass)
+ BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::GPRCRegisterClass)
+ BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else
+ abort();
}
void
AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx) const{
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const {
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
- //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
- BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addImm(FrameIdx * 8).addReg(Alpha::R30);
- // assert(0 && "TODO");
+ if (EnableAlphaLSMark)
+ BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
+ .addImm(getUID());
+ if (RC == Alpha::F4RCRegisterClass)
+ BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::F8RCRegisterClass)
+ BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::GPRCRegisterClass)
+ BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else
+ abort();
}
+MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
+ unsigned OpNum,
+ int FrameIndex) const {
+ // Make sure this is a reg-reg copy.
+ unsigned Opc = MI->getOpcode();
+
+ switch(Opc) {
+ default:
+ break;
+ case Alpha::BIS:
+ case Alpha::CPYSS:
+ case Alpha::CPYST:
+ if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
+ if (OpNum == 0) { // move -> store
+ unsigned InReg = MI->getOperand(1).getReg();
+ Opc = (Opc == Alpha::BIS) ? Alpha::STQ :
+ ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
+ return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ } else { // load -> move
+ unsigned OutReg = MI->getOperand(0).getReg();
+ Opc = (Opc == Alpha::BIS) ? Alpha::LDQ :
+ ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
+ return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
+ }
+ }
+ break;
+ }
+ return 0;
+}
+
+
void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
// std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (RC == Alpha::GPRCRegisterClass) {
BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (RC == Alpha::FPRCRegisterClass) {
- BuildMI(MBB, MI, Alpha::CPYS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- } else {
+ } else if (RC == Alpha::F4RCRegisterClass) {
+ BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else if (RC == Alpha::F8RCRegisterClass) {
+ BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
}
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
if (hasFP(MF)) {
- assert(0 && "TODO");
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
// <amt>'
Amount = (Amount+Align-1)/Align*Align;
MachineInstr *New;
-// if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
-// New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
-// .addZImm(Amount);
-// } else {
-// assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
-// New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
-// .addZImm(Amount);
-// }
+ if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
+ New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+ .addImm(-Amount).addReg(Alpha::R30);
+ } else {
+ assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
+ New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+ .addImm(Amount).addReg(Alpha::R30);
+ }
// Replace the pseudo instruction with a new instruction...
MBB.insert(I, New);
MBB.erase(I);
}
+//Alpha has a slightly funny stack:
+//Args
+//<- incoming SP
+//fixed locals (and spills, callee saved, etc)
+//<- FP
+//variable locals
+//<- SP
+
void
AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
- assert(0 && "TODO");
-// unsigned i = 0;
-// MachineInstr &MI = *II;
-// MachineBasicBlock &MBB = *MI.getParent();
-// MachineFunction &MF = *MBB.getParent();
-
-// while (!MI.getOperand(i).isFrameIndex()) {
-// ++i;
-// assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
-// }
-
-// int FrameIndex = MI.getOperand(i).getFrameIndex();
-
-// // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
-// MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
-
-// // Take into account whether it's an add or mem instruction
-// unsigned OffIdx = (i == 2) ? 1 : 2;
-
-// // Now add the frame object offset to the offset from r1.
-// int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
-// MI.getOperand(OffIdx).getImmedValue();
-
-// // If we're not using a Frame Pointer that has been set to the value of the
-// // SP before having the stack size subtracted from it, then add the stack size
-// // to Offset to get the correct offset.
-// Offset += MF.getFrameInfo()->getStackSize();
-
-// if (Offset > 32767 || Offset < -32768) {
-// // Insert a set of r0 with the full offset value before the ld, st, or add
-// MachineBasicBlock *MBB = MI.getParent();
-// MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
-// MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
-// .addImm(Offset));
-// // convert into indexed form of the instruction
-// // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
-// // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
-// unsigned NewOpcode =
-// const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
-// assert(NewOpcode && "No indexed form of load or store available!");
-// MI.setOpcode(NewOpcode);
-// MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
-// MI.SetMachineOperandReg(2, PPC::R0);
-// } else {
-// MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
-// Offset);
-// }
+ unsigned i = 0;
+ MachineInstr &MI = *II;
+ MachineBasicBlock &MBB = *MI.getParent();
+ MachineFunction &MF = *MBB.getParent();
+ bool FP = hasFP(MF);
+
+ while (!MI.getOperand(i).isFrameIndex()) {
+ ++i;
+ assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
+ }
+
+ int FrameIndex = MI.getOperand(i).getFrameIndex();
+
+ // Add the base register of R30 (SP) or R15 (FP).
+ MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30);
+
+ // Now add the frame object offset to the offset from the virtual frame index.
+ int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
+
+ DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
+
+ Offset += MF.getFrameInfo()->getStackSize();
+
+ DEBUG(std::cerr << "Corrected Offset " << Offset <<
+ " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
+
+ if (Offset > IMM_HIGH || Offset < IMM_LOW) {
+ DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n");
+ //so in this case, we need to use a temporary register, and move the original
+ //inst off the SP/FP
+ //fix up the old:
+ MI.SetMachineOperandReg(i + 1, Alpha::R28);
+ MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed,
+ getLower16(Offset));
+ //insert the new
+ MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
+ .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
+ MBB.insert(II, nMI);
+ } else {
+ MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
+ }
}
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
- MachineInstr *MI;
-
+ bool FP = hasFP(MF);
+
+ static int curgpdist = 0;
+
//handle GOP offset
- MI = BuildMI(Alpha::LDGP, 0);
- MBB.insert(MBBI, MI);
+ BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
+ .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
+ .addReg(Alpha::R27).addImm(++curgpdist);
+ BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
+ .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
+ .addReg(Alpha::R29).addImm(curgpdist);
+
+ //evil const_cast until MO stuff setup to handle const
+ BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
// Get the number of bytes to allocate from the FrameInfo
- unsigned NumBytes = MFI->getStackSize();
+ long NumBytes = MFI->getStackSize();
+
+ if (MFI->hasCalls() && !FP) {
+ // We reserve argument space for call sites in the function immediately on
+ // entry to the current function. This eliminates the need for add/sub
+ // brackets around call sites.
+ //If there is a frame pointer, then we don't do this
+ NumBytes += MFI->getMaxCallFrameSize();
+ DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize()
+ << " to the stack due to calls\n");
+ }
+
+ if (FP)
+ NumBytes += 8; //reserve space for the old FP
// Do we need to allocate space on the stack?
if (NumBytes == 0) return;
- // Add the size of R30 to NumBytes size for the store of R30 to the
- // stack
-// std::cerr << "Spillsize of R30 is " << getSpillSize(Alpha::R30) << "\n";
-// NumBytes = NumBytes + getSpillSize(Alpha::R30)/8;
+ unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
+ NumBytes = (NumBytes+Align-1)/Align*Align;
// Update frame info to pretend that this is part of the stack...
MFI->setStackSize(NumBytes);
-
+
// adjust stack pointer: r30 -= numbytes
-
- if (NumBytes <= 32767) {
- MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-NumBytes).addReg(Alpha::R30);
- MBB.insert(MBBI, MI);
- } else if ((unsigned long)NumBytes <= (unsigned long)32767 * (unsigned long)65536) {
- long y = NumBytes / 65536;
- if (NumBytes % 65536 > 32767)
- ++y;
- MI=BuildMI(Alpha::LDAH, 2, Alpha::R30).addImm(-y).addReg(Alpha::R30);
- MBB.insert(MBBI, MI);
- MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-(NumBytes - y * 65536)).addReg(Alpha::R30);
- MBB.insert(MBBI, MI);
+ NumBytes = -NumBytes;
+ if (NumBytes >= IMM_LOW) {
+ BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
+ .addReg(Alpha::R30);
+ } else if (getUpper16(NumBytes) >= IMM_LOW) {
+ BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes))
+ .addReg(Alpha::R30);
+ BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes))
+ .addReg(Alpha::R30);
} else {
std::cerr << "Too big a stack frame at " << NumBytes << "\n";
abort();
}
+
+ //now if we need to, save the old FP and set the new
+ if (FP)
+ {
+ if (EnableAlphaLSMark)
+ BuildMI(MBB, MBBI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
+ .addImm(getUID());
+ BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
+ //this must be the last instr in the prolog
+ BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30);
+ }
+
}
void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- MachineInstr *MI;
- assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN) &&
- "Can only insert epilog into returning blocks");
-
+ assert(MBBI->getOpcode() == Alpha::RETDAG
+ && "Can only insert epilog into returning blocks");
+
+ bool FP = hasFP(MF);
+
// Get the number of bytes allocated from the FrameInfo...
- unsigned NumBytes = MFI->getStackSize();
+ long NumBytes = MFI->getStackSize();
+
+ //now if we need to, restore the old FP
+ if (FP)
+ {
+ //copy the FP into the SP (discards allocas)
+ BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R30).addReg(Alpha::R15)
+ .addReg(Alpha::R15);
+ //restore the FP
+ if (EnableAlphaLSMark)
+ BuildMI(MBB, MBBI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
+ .addImm(getUID());
+ BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
+ }
- if (NumBytes != 0)
+ if (NumBytes != 0)
{
- if (NumBytes <= 32767) {
- MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes).addReg(Alpha::R30);
- MBB.insert(MBBI, MI);
- } else if ((unsigned long)NumBytes <= (unsigned long)32767 * (unsigned long)65536) {
- long y = NumBytes / 65536;
- if (NumBytes % 65536 > 32767)
- ++y;
- MI=BuildMI(Alpha::LDAH, 2, Alpha::R30).addImm(y).addReg(Alpha::R30);
- MBB.insert(MBBI, MI);
- MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes - y * 65536).addReg(Alpha::R30);
- MBB.insert(MBBI, MI);
+ if (NumBytes <= IMM_HIGH) {
+ BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
+ .addReg(Alpha::R30);
+ } else if (getUpper16(NumBytes) <= IMM_HIGH) {
+ BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30)
+ .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
+ BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30)
+ .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
} else {
std::cerr << "Too big a stack frame at " << NumBytes << "\n";
abort();
#include "AlphaGenRegisterInfo.inc"
-const TargetRegisterClass*
-AlphaRegisterInfo::getRegClassForType(const Type* Ty) const {
- switch (Ty->getTypeID()) {
- default: assert(0 && "Invalid type to getClass!");
- case Type::BoolTyID:
- case Type::SByteTyID:
- case Type::UByteTyID:
- case Type::ShortTyID:
- case Type::UShortTyID:
- case Type::IntTyID:
- case Type::UIntTyID:
- case Type::PointerTyID:
- case Type::LongTyID:
- case Type::ULongTyID: return &GPRCInstance;
-
- case Type::FloatTyID:
- case Type::DoubleTyID: return &FPRCInstance;
- }
-}
-
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
{
std::string s(RegisterDescriptors[reg].Name);
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