def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
SDTCisFP<1>, SDTCisFP<0>
]>;
+def SDTLoadA : SDTypeProfile<1, 6, [ // load
+ SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
+]>;
+def SDTStoreA : SDTypeProfile<0, 7, [ // load
+ SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
+]>;
-def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
-def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
-def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
-def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
-def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
+def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
+def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
+def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
+def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
+def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
+def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
+def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
+def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
+def Alpha_ldq : SDNode<"AlphaISD::LDQ_", SDTLoadA, [SDNPHasChain]>;
+def Alpha_ldt : SDNode<"AlphaISD::LDT_", SDTLoadA, [SDNPHasChain]>;
+def Alpha_lds : SDNode<"AlphaISD::LDS_", SDTLoadA, [SDNPHasChain]>;
+def Alpha_ldl : SDNode<"AlphaISD::LDL_", SDTLoadA, [SDNPHasChain]>;
+def Alpha_ldwu : SDNode<"AlphaISD::LDWU_", SDTLoadA, [SDNPHasChain]>;
+def Alpha_ldbu : SDNode<"AlphaISD::LDBU_", SDTLoadA, [SDNPHasChain]>;
+def Alpha_stq : SDNode<"AlphaISD::STQ_", SDTStoreA, [SDNPHasChain]>;
+def Alpha_stl : SDNode<"AlphaISD::STL_", SDTStoreA, [SDNPHasChain]>;
+def Alpha_stw : SDNode<"AlphaISD::STW_", SDTStoreA, [SDNPHasChain]>;
+def Alpha_stb : SDNode<"AlphaISD::STB_", SDTStoreA, [SDNPHasChain]>;
+def Alpha_sts : SDNode<"AlphaISD::STS_", SDTStoreA, [SDNPHasChain]>;
+def Alpha_stt : SDNode<"AlphaISD::STT_", SDTStoreA, [SDNPHasChain]>;
// These are target-independent nodes, but have target-specific formats.
def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq,[SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq,[SDNPHasChain]>;
-
//********************
//Paterns for matching
//********************
-def invX : SDNodeXForm<imm, [{
+def invX : SDNodeXForm<imm, [{ //invert
return getI64Imm(~N->getValue());
}]>;
-def immUExt8 : PatLeaf<(imm), [{
- // immUExt8 predicate - True if the immediate fits in a 8-bit zero extended
- // field. Used by instructions like 'addi'.
- return (unsigned long)N->getValue() == (unsigned char)N->getValue();
+def negX : SDNodeXForm<imm, [{ //negate
+ return getI64Imm(~N->getValue() + 1);
}]>;
-def immUExt8inv : PatLeaf<(imm), [{
- // immUExt8inv predicate - True if the inverted immediate fits in a 8-bit zero extended
- // field. Used by instructions like 'ornoti'.
- return (unsigned long)~N->getValue() == (unsigned char)~N->getValue();
-}], invX>;
-def immSExt16 : PatLeaf<(imm), [{
- // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
- // field. Used by instructions like 'lda'.
- return (int)N->getValue() == (short)N->getValue();
+def SExt32 : SDNodeXForm<imm, [{ //signed extend int to long
+ return getI64Imm(((int64_t)N->getValue() << 32) >> 32);
+}]>;
+def SExt16 : SDNodeXForm<imm, [{ //signed extend int to long
+ return getI64Imm(((int64_t)N->getValue() << 48) >> 48);
+}]>;
+def LL16 : SDNodeXForm<imm, [{ //lda part of constant
+ return getI64Imm(get_lda16(N->getValue()));
+}]>;
+def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
+ return getI64Imm(get_ldah16(N->getValue()));
+}]>;
+def iZAPX : SDNodeXForm<imm, [{ // get imm to ZAPi
+ return getI64Imm(get_zapImm((uint64_t)N->getValue()));
}]>;
-def iZAPX : SDNodeXForm<imm, [{
- // Transformation function: get the imm to ZAPi
- uint64_t UImm = (uint64_t)N->getValue();
- unsigned int build = 0;
- for(int i = 0; i < 8; ++i)
- {
- if ((UImm & 0x00FF) == 0x00FF)
- build |= 1 << i;
- else if ((UImm & 0x00FF) != 0)
- { build = 0; break; }
- UImm >>= 8;
- }
- return getI64Imm(build);
+def immUExt8 : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
+ return (uint64_t)N->getValue() == (uint8_t)N->getValue();
+}]>;
+def immUExt8inv : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field
+ return (uint64_t)~N->getValue() == (uint8_t)~N->getValue();
+}], invX>;
+def immUExt8neg : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field
+ return ((uint64_t)~N->getValue() + 1) == (uint8_t)((uint64_t)~N->getValue() + 1);
+}], negX>;
+def immSExt16 : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field
+ return ((int64_t)N->getValue() << 48) >> 48 == (int64_t)N->getValue();
}]>;
-def immZAP : PatLeaf<(imm), [{
- // immZAP predicate - True if the immediate fits is suitable for use in a
- // ZAP instruction
- uint64_t UImm = (uint64_t)N->getValue();
- unsigned int build = 0;
- for(int i = 0; i < 8; ++i)
- {
- if ((UImm & 0x00FF) == 0x00FF)
- build |= 1 << i;
- else if ((UImm & 0x00FF) != 0)
- { build = 0; break; }
- UImm >>= 8;
- }
+def immSExt16int : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field
+ return ((int64_t)N->getValue() << 48) >> 48 == ((int64_t)N->getValue() << 32) >> 32;
+}], SExt16>;
+def immZAP : PatLeaf<(imm), [{ //imm is good for zapi
+ uint64_t build = get_zapImm((uint64_t)N->getValue());
return build != 0;
}], iZAPX>;
-
+def immFPZ : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
+ return true;
+}]>;
def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
def add4 : PatFrag<(ops node:$op1, node:$op2),
def sub8 : PatFrag<(ops node:$op1, node:$op2),
(sub (shl node:$op1, 3), node:$op2)>;
- // //#define FP $15
- // //#define RA $26
- // //#define PV $27
- // //#define GP $29
- // //#define SP $30
-def PHI : PseudoInstAlpha<(ops variable_ops), "#phi", []>;
+//Pseudo ops for selection
def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA",
[(set GPRC:$RA, (undef))]>;
[(set F8RC:$RA, (undef))]>;
def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>;
+
let isLoad = 1, hasCtrlDep = 1 in {
def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt",
[(callseq_start imm:$amt)]>;
def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "; ADJDOWN $amt",
[(callseq_end imm:$amt)]>;
}
-def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n", []>;
+def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$$$TARGET..ng:\n", []>;
def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
- "LSMARKER$$$i$$$j$$$k$$$m:\n",[]>;
-
-//*****************
-//These are shortcuts, the assembler expands them
-//*****************
-//AT = R28
-//T0-T7 = R1 - R8
-//T8-T11 = R22-R25
-
-//An even better improvement on the Int = SetCC(FP): SelectCC!
-//These are evil because they hide control flow in a MBB
-//really the ISel should emit multiple MBB
-let isTwoAddress = 1 in {
-//Conditional move of an int based on a FP CC
- def CMOVEQ_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
- "fbne $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
- def CMOVEQi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
- "fbne $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n", []>;
-
- def CMOVNE_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
- "fbeq $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
- def CMOVNEi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
- "fbeq $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n", []>;
-//Conditional move of an FP based on a Int CC
- def FCMOVEQ_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
- "bne $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
- def FCMOVNE_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
- "beq $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n", []>;
-}
+ "LSMARKER$$$i$$$j$$$k$$$m:", []>;
+
//***********************
//Real instructions
//Operation Form:
//conditional moves, int
-def CMOVEQi : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
-def CMOVGEi : OForm4L< 0x11, 0x46, "cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
-def CMOVGTi : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
-def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
-def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
-def CMOVLEi : OForm4L< 0x11, 0x64, "cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
-def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
-def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
-
-let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, GPRC:$RTRUE, GPRC:$RCOND) in {
+
def CMOVLBC : OForm4< 0x11, 0x16, "cmovlbc $RCOND,$RTRUE,$RDEST",
[(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))]>;
def CMOVLBS : OForm4< 0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST",
def CMOVGT : OForm4< 0x11, 0x66, "cmovgt $RCOND,$RTRUE,$RDEST",
[(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
def CMOVLE : OForm4< 0x11, 0x64, "cmovle $RCOND,$RTRUE,$RDEST",
- [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
+ [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
def CMOVLT : OForm4< 0x11, 0x44, "cmovlt $RCOND,$RTRUE,$RDEST",
[(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RTRUE,$RDEST",
[(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))]>;
-}
+
+def CMOVEQi : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVGEi : OForm4L< 0x11, 0x46, "cmovge $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVGTi : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVLEi : OForm4L< 0x11, 0x64, "cmovle $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST",
+ [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))]>;
+
//FIXME: fold setcc with select for all cases. clearly I need patterns for inverted conditions
// and constants (which require inverted conditions as legalize puts the constant in the
// wrong field for the instruction definition
def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
- (CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
+ (CMOVNE GPRC:$src2, GPRC:$src1, GPRC:$which)>;
+def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2),
+ (CMOVEQi GPRC:$src1, immUExt8:$src2, GPRC:$which)>;
def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
[(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>;
def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC",
[(set GPRC:$RC, (xor GPRC:$RA, immUExt8inv:$L))]>;
-//def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", []>; //Extract byte low
+def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC",
+ [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 255))]>;
+def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC",
+ [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 65535))]>;
+def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC",
+ [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 4294967295))]>;
+
//def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
//def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
//def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high
-//def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", []>; //Extract longword low
//def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low
//def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high
//def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high
//def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low
//def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high
//def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high
-//def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", []>; //Extract word low
//def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low
+
//def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC", []>; //Implementation version
//def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC", []>; //Implementation version
//def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low
def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC",
[(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))]>;
def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC",
- [(set GPRC:$RC, (intop (sub8 GPRC:$RA, immUExt8:$L)))]>;
+ [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8neg:$L)))]>;
def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC",
[(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>;
def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC",
- [(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>;
+ [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8neg:$L))]>;
def SEXTB : OForm2<0x1C, 0x00, "sextb $RB,$RC",
[(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>;
def SEXTW : OForm2<0x1C, 0x01, "sextw $RB,$RC",
def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC",
[(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))]>;
def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC",
- [(set GPRC:$RC, (intop (sub GPRC:$RA, immUExt8:$L)))]>;
+ [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8neg:$L)))]>;
def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
[(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>;
def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
- [(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>;
+ [(set GPRC:$RC, (add GPRC:$RA, immUExt8neg:$L))]>;
def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC",
[(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>;
def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC",
def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
-let isReturn = 1, isTerminator = 1 in
- def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine
-//DAG Version:
-let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in
+let isReturn = 1, isTerminator = 1, noResults = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in
def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1">; //Return from subroutine
def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump
-let isCall = 1,
+let isCall = 1, noResults = 1, Ra = 26,
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
- R20, R21, R22, R23, R24, R25, R27, R28, R29,
+ R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
- def JSR : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
- def BSR : BForm<0x34, "bsr $RA,$DISP">; //Branch to subroutine
+ def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", []>; //Branch to subroutine
}
-let isCall = 1,
+let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
- def JSRDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine
+ def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0">; //Jump to subroutine
}
-let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
- def JSRs : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
-let isCall = 1, Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
- def JSRsDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0">; //Jump to div or rem
+let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0,
+ Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
+ def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0">; //Jump to div or rem
+
def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
-def BR : BForm<0x30, "br $RA,$DISP">; //Branch
-
-def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch
-
-//Stores, int
-def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
-def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
-def STL : MForm<0x2C, "stl $RA,$DISP($RB)">; // Store longword
-def STQ : MForm<0x2D, "stq $RA,$DISP($RB)">; //Store quadword
-
-//Loads, int
-def LDL : MForm<0x28, "ldl $RA,$DISP($RB)">; // Load sign-extended longword
-def LDQ : MForm<0x29, "ldq $RA,$DISP($RB)">; //Load quadword
-def LDBU : MForm<0x0A, "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
-def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
-
-//Stores, float
-let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def STS : MFormAlt<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
-let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def STT : MFormAlt<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
-
-//Loads, float
-let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def LDS : MFormAlt<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
-let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def LDT : MFormAlt<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
+
+let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
+def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
+ [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
+def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
+ [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
+def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
+ [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))]>;
+def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
+ [(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32))]>;
+def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
+ [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))]>;
+def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
+ [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8))]>;
+def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
+ [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))]>;
+def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
+ [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16))]>;
+def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
+ [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)]>;
+def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
+ [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8)]>;
+def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
+ [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i16)]>;
+def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
+ [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16)]>;
+def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
+ [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i32)]>;
+def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
+ [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32)]>;
+def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
+ [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
+ [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
//Load address
-def LDA : MForm<0x08, "lda $RA,$DISP($RB)">; //Load address
-def LDAH : MForm<0x09, "ldah $RA,$DISP($RB)">; //Load address high
+def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
+ [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
+ [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>; //Load address
+def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
+ []>; //Load address high
+def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
+ [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))]>; //Load address high
+}
+let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
+def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
+ [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
+ [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
+def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
+ [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
+def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
+ [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
+}
+let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
+def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
+ [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
+def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
+ [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
+def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
+ [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
+def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
+ [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
+}
-//Loads, int, Rellocated Low form
-def LDLr : MForm<0x28, "ldl $RA,$DISP($RB)\t\t!gprellow">; // Load sign-extended longword
-def LDQr : MForm<0x29, "ldq $RA,$DISP($RB)\t\t!gprellow">; //Load quadword
-def LDBUr : MForm<0x0A, "ldbu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extended byte
-def LDWUr : MForm<0x0C, "ldwu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extended word
-//Loads, float, Rellocated Low form
-let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def LDSr : MFormAlt<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
-let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def LDTr : MFormAlt<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
+//constpool rels
+def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+ (LDQr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)),
+ (LDLr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)),
+ (LDBUr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)),
+ (LDWUr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
+ (LDAr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
+ (LDAHr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(f32 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+ (LDSr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(f64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+ (LDTr tconstpool:$DISP, GPRC:$RB)>;
+
+
+//misc ext patterns
+def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
+ (LDBU immSExt16:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i16)),
+ (LDWU immSExt16:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i32)),
+ (LDL immSExt16:$DISP, GPRC:$RB)>;
+
+//0 disp patterns
+def : Pat<(i64 (load GPRC:$addr)),
+ (LDQ 0, GPRC:$addr)>;
+def : Pat<(f64 (load GPRC:$addr)),
+ (LDT 0, GPRC:$addr)>;
+def : Pat<(f32 (load GPRC:$addr)),
+ (LDS 0, GPRC:$addr)>;
+def : Pat<(i64 (sextload GPRC:$addr, i32)),
+ (LDL 0, GPRC:$addr)>;
+def : Pat<(i64 (zextload GPRC:$addr, i16)),
+ (LDWU 0, GPRC:$addr)>;
+def : Pat<(i64 (zextload GPRC:$addr, i8)),
+ (LDBU 0, GPRC:$addr)>;
+def : Pat<(i64 (extload GPRC:$addr, i8)),
+ (LDBU 0, GPRC:$addr)>;
+def : Pat<(i64 (extload GPRC:$addr, i16)),
+ (LDWU 0, GPRC:$addr)>;
+def : Pat<(i64 (extload GPRC:$addr, i32)),
+ (LDL 0, GPRC:$addr)>;
+
+def : Pat<(store GPRC:$DATA, GPRC:$addr),
+ (STQ GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(store F8RC:$DATA, GPRC:$addr),
+ (STT F8RC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(store F4RC:$DATA, GPRC:$addr),
+ (STS F4RC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i32),
+ (STL GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i16),
+ (STW GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
+ (STB GPRC:$DATA, 0, GPRC:$addr)>;
-//Load address, rellocated low and high form
-def LDAr : MForm<0x08, "lda $RA,$DISP($RB)\t\t!gprellow">; //Load address
-def LDAHr : MForm<0x09, "ldah $RA,$DISP($RB)\t\t!gprelhigh">; //Load address high
//load address, rellocated gpdist form
-def LDAg : MgForm<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
-def LDAHg : MgForm<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
-
+let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
+def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load address
+def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load address
+}
//Load quad, rellocated literal form
-def LDQl : MForm<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
-
-//Stores, int
-def STBr : MForm<0x0E, "stb $RA,$DISP($RB)\t\t!gprellow">; // Store byte
-def STWr : MForm<0x0D, "stw $RA,$DISP($RB)\t\t!gprellow">; // Store word
-def STLr : MForm<0x2C, "stl $RA,$DISP($RB)\t\t!gprellow">; // Store longword
-def STQr : MForm<0x2D, "stq $RA,$DISP($RB)\t\t!gprellow">; //Store quadword
-
-//Stores, float
-let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def STSr : MFormAlt<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
-let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
-def STTr : MFormAlt<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
-
+let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
+def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
+ [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))]>;
+def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
+ (LDQl texternalsym:$ext, GPRC:$RB)>;
+
+
+//Various tracked versions
+let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB,
+ s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in {
+def LDQlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldq $RA,$DISP($RB)",
+ [(set GPRC:$RA, (Alpha_ldq imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
+def LDLlbl : MForm<0x28, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldl $RA,$DISP($RB)",
+ [(set GPRC:$RA, (Alpha_ldl imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
+def LDBUlbl : MForm<0x0A, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldbu $RA,$DISP($RB)",
+ [(set GPRC:$RA, (Alpha_ldwu imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
+def LDWUlbl : MForm<0x0C, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldwu $RA,$DISP($RB)",
+ [(set GPRC:$RA, (Alpha_ldbu imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
+
+def STBlbl : MForm<0x0E, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stb $RA,$DISP($RB)",
+ [(Alpha_stb GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
+def STWlbl : MForm<0x0D, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stw $RA,$DISP($RB)",
+ [(Alpha_stw GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
+def STLlbl : MForm<0x2C, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stl $RA,$DISP($RB)",
+ [(Alpha_stl GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
+def STQlbl : MForm<0x2D, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stq $RA,$DISP($RB)",
+ [(Alpha_stq GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
+}
-//Branches, int
-def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
-def BGE : BForm<0x3E, "bge $RA,$DISP">; //Branch if >= zero
-def BGT : BForm<0x3F, "bgt $RA,$DISP">; //Branch if > zero
-def BLBC : BForm<0x38, "blbc $RA,$DISP">; //Branch if low bit clear
-def BLBS : BForm<0x3C, "blbs $RA,$DISP">; //Branch if low bit set
-def BLE : BForm<0x3B, "ble $RA,$DISP">; //Branch if <= zero
-def BLT : BForm<0x3A, "blt $RA,$DISP">; //Branch if < zero
-def BNE : BForm<0x3D, "bne $RA,$DISP">; //Branch if != zero
+let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB,
+ s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
+def LDTlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldt $RA,$DISP($RB)",
+ [(set F8RC:$RA, (Alpha_ldt imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-//Branches, float
-def FBEQ : FBForm<0x31, "fbeq $RA,$DISP">; //Floating branch if = zero
-def FBGE : FBForm<0x36, "fbge $RA,$DISP">; //Floating branch if >= zero
-def FBGT : FBForm<0x37, "fbgt $RA,$DISP">; //Floating branch if > zero
-def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero
-def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
-def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
+let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB,
+ s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
+def LDSlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t lds $RA,$DISP($RB)",
+ [(set F4RC:$RA, (Alpha_lds imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
//TODO: Add lots more FP patterns
//conditional moves, floats
-let OperandList = (ops F4RC:$RDEST, F4RC:$RSRC2, F4RC:$RSRC, F8RC:$RCOND),
+let OperandList = (ops F4RC:$RDEST, F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND),
isTwoAddress = 1 in {
-def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
-def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
-def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
-def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
-def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
-def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST",[]>; //FCMOVE if != zero
}
//conditional moves, doubles
-let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
+let OperandList = (ops F8RC:$RDEST, F8RC:$RFALSE, F8RC:$RTRUE, F8RC:$RCOND),
isTwoAddress = 1 in {
-def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
-def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
-def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
-def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
-def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
-def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST", []>;
+def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST", []>;
+def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST", []>;
+def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST", []>;
+def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST", []>;
+def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST", []>;
}
+//misc FP selects
+//Select double
+def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
+ (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
+def : Pat<(select (setne F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
+ (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
+def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
+ (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
+def : Pat<(select (setge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
+ (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
+def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
+ (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
+def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
+ (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
+//Select single
+def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
+ (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
+def : Pat<(select (setne F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
+ (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
+def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
+ (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
+def : Pat<(select (setge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
+ (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
+def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
+ (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
+def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
+ (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
+
let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
[(set F4RC:$RC, (fround F8RC:$RB))]>;
+
+/////////////////////////////////////////////////////////
+//Branching
+/////////////////////////////////////////////////////////
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
+let Ra = 31 in
+def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>;
+
+//Branches, int
+def BEQ : BForm<0x39, "beq $RA,$DISP",
+ [(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
+def BGE : BForm<0x3E, "bge $RA,$DISP",
+ [(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
+def BGT : BForm<0x3F, "bgt $RA,$DISP",
+ [(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
+def BLBC : BForm<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
+def BLBS : BForm<0x3C, "blbs $RA,$DISP",
+ [(brcond (and GPRC:$RA, 1), bb:$DISP)]>;
+def BLE : BForm<0x3B, "ble $RA,$DISP",
+ [(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
+def BLT : BForm<0x3A, "blt $RA,$DISP",
+ [(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
+def BNE : BForm<0x3D, "bne $RA,$DISP",
+ [(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
+
+//Branches, float
+def FBEQ : FBForm<0x31, "fbeq $RA,$DISP",
+ [(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)]>;
+def FBGE : FBForm<0x36, "fbge $RA,$DISP",
+ [(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)]>;
+def FBGT : FBForm<0x37, "fbgt $RA,$DISP",
+ [(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)]>;
+def FBLE : FBForm<0x33, "fble $RA,$DISP",
+ [(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)]>;
+def FBLT : FBForm<0x32, "fblt $RA,$DISP",
+ [(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)]>;
+def FBNE : FBForm<0x35, "fbne $RA,$DISP",
+ [(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)]>;
+}
+
+def : Pat<(brcond GPRC:$RA, bb:$DISP), (BNE GPRC:$RA, bb:$DISP)>;
+def : Pat<(brcond (setne GPRC:$RA, GPRC:$RB), bb:$DISP),
+ (BEQ (CMPEQ GPRC:$RA, GPRC:$RB), bb:$DISP)>;
+def : Pat<(brcond (setne GPRC:$RA, immUExt8:$L), bb:$DISP),
+ (BEQ (CMPEQi GPRC:$RA, immUExt8:$L), bb:$DISP)>;
+def : Pat<(brcond (seteq F8RC:$RA, F8RC:$RB), bb:$DISP),
+ (FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
+def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),
+ (FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
+def : Pat<(brcond (setle F8RC:$RA, F8RC:$RB), bb:$DISP),
+ (FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
+def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),
+ (FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
+def : Pat<(brcond (setge F8RC:$RA, F8RC:$RB), bb:$DISP),
+ (FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
+def : Pat<(brcond (setne F8RC:$RA, F8RC:$RB), bb:$DISP),
+ (FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
+
+//End Branches
+
//S_floating : IEEE Single
//T_floating : IEEE Double
//Constant handling
def immConst2Part : PatLeaf<(imm), [{
- // immZAP predicate - True if the immediate fits is suitable for use in a
- // ZAP instruction
+ //true if imm fits in a LDAH LDA pair
int64_t val = (int64_t)N->getValue();
- return (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &
- val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT);
-}]>;
-
-//TODO: factor this out
-def LL16 : SDNodeXForm<imm, [{
-int64_t l = N->getValue();
- int64_t y = l / IMM_MULT;
- if (l % IMM_MULT > IMM_HIGH)
- ++y;
- return getI64Imm(l - y * IMM_MULT);
-}]>;
-//TODO: factor this out
-def LH16 : SDNodeXForm<imm, [{
-int64_t l = N->getValue();
- int64_t y = l / IMM_MULT;
- if (l % IMM_MULT > IMM_HIGH)
- ++y;
- return getI64Imm(y);
+ return (val <= IMM_FULLHIGH && val >= IMM_FULLLOW);
}]>;
+def immConst2PartInt : PatLeaf<(imm), [{
+ //true if imm fits in a LDAH LDA pair with zeroext
+ uint64_t uval = N->getValue();
+ int32_t val32 = (int32_t)uval;
+ return ((uval >> 32) == 0 && //empty upper bits
+ val32 <= IMM_FULLHIGH);
+// val32 >= IMM_FULLLOW + IMM_LOW * IMM_MULT); //Always True
+}], SExt32>;
def : Pat<(i64 immConst2Part:$imm),
(LDA (LL16 immConst2Part:$imm), (LDAH (LH16 immConst2Part:$imm), R31))>;
def : Pat<(i64 immSExt16:$imm),
(LDA immSExt16:$imm, R31)>;
+def : Pat<(i64 immSExt16int:$imm),
+ (ZAPNOTi (LDA (SExt16 immSExt16int:$imm), R31), 15)>;
+def : Pat<(i64 immConst2PartInt:$imm),
+ (ZAPNOTi (LDA (LL16 (SExt32 immConst2PartInt:$imm)),
+ (LDAH (LH16 (SExt32 immConst2PartInt:$imm)), R31)), 15)>;
+
+
//TODO: I want to just define these like this!
//def : Pat<(i64 0),
// (R31)>;
projects / oota-llvm.git / blobdiff