#include "AlphaInstrInfo.h"
#include "AlphaGenInstrInfo.inc"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include <iostream>
using namespace llvm;
AlphaInstrInfo::AlphaInstrInfo()
- : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { }
+ : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])),
+ RI(*this) { }
bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == Alpha::BIS ||
+ if (oc == Alpha::BISr ||
oc == Alpha::CPYSS ||
oc == Alpha::CPYST ||
oc == Alpha::CPYSSt ||
oc == Alpha::CPYSTs) {
// or r1, r2, r2
// cpys(s|t) r1 r2 r2
- assert(MI.getNumOperands() == 3 &&
+ assert(MI.getNumOperands() >= 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isRegister() &&
}
}
-void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond)const{
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);
+ BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
else // Conditional branch
if (isAlphaIntCondCode(Cond[0].getImm()))
- BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
+ BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
- BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
+ BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
- return;
+ return 1;
}
// Two-way Conditional Branch.
if (isAlphaIntCondCode(Cond[0].getImm()))
- BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
+ BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
- BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
+ BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB);
+ BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
+ return 2;
}
static unsigned AlphaRevCondCode(unsigned Opcode) {
return true;
}
-void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
+unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator I = MBB.end();
- if (I == MBB.begin()) return;
+ if (I == MBB.begin()) return 0;
--I;
if (I->getOpcode() != Alpha::BR &&
I->getOpcode() != Alpha::COND_BRANCH_I &&
I->getOpcode() != Alpha::COND_BRANCH_F)
- return;
+ return 0;
// Remove the branch.
I->eraseFromParent();
I = MBB.end();
- if (I == MBB.begin()) return;
+ if (I == MBB.begin()) return 1;
--I;
if (I->getOpcode() != Alpha::COND_BRANCH_I &&
I->getOpcode() != Alpha::COND_BRANCH_F)
- return;
+ return 1;
// Remove the branch.
I->eraseFromParent();
+ return 2;
}
void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
}