Rename SDOperand to SDValue.

[oota-llvm.git] / lib / Target / Alpha / AlphaInstrFormats.td

diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td
index 663562948d47adf5ec7b5cee580ae976f6c99471..6eb59e0eeca05934d4c323f41ba386484f5d22a5 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrFormats.td
+++ b/lib/Target/Alpha/AlphaInstrFormats.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -22,6 +22,7 @@ def s14imm  : Operand<i64>;
 def s16imm  : Operand<i64>;
 def s21imm  : Operand<i64>;
 def s64imm  : Operand<i64>;
+def u64imm  : Operand<i64>;
 
 //===----------------------------------------------------------------------===//
 // Instruction format superclass
@@ -37,11 +38,10 @@ class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
 
 
 //3.3.1
-class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> 
+class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> 
         : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let isStore = store;
-  let isLoad = load;
+  let isSimpleLoad = load;
   let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
 
   bits<5> Ra;
@@ -56,11 +56,20 @@ class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
         : InstAlpha<opcode, asmstr, itin> {    
   bits<5> Ra;
 
-  let OperandList = (ops GPRC:$RA);
+  let OutOperandList = (ops GPRC:$RA);
+  let InOperandList = (ops);
   let Inst{25-21} = Ra;
   let Inst{20-16} = 0;
   let Inst{15-0} = fc;
 }
+class MfcPForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> 
+        : InstAlpha<opcode, asmstr, itin> {    
+  let OutOperandList = (ops);
+  let InOperandList = (ops);
+  let Inst{25-21} = 0;
+  let Inst{20-16} = 0;
+  let Inst{15-0} = fc;
+}
 
 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
     : InstAlpha<opcode, asmstr, itin> {
@@ -68,46 +77,53 @@ class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass
   bits<5> Rb;
   bits<14> disp;
 
-  let OperandList = OL;
+  let OutOperandList = (ops);
+  let InOperandList = OL;
 
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
   let Inst{15-14} = TB;
   let Inst{13-0} = disp;
 }
-
-//3.3.2
-def target : Operand<OtherVT> {}
-let isBranch = 1, isTerminator = 1 in
-class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
     : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OperandList = (ops target:$DISP);
+  let Pattern=pattern;
   bits<5> Ra;
-  bits<21> disp;
+  bits<5> Rb;
+  bits<14> disp;
+
+  let OutOperandList = (ops);
+  let InOperandList = OL;
 
   let Inst{25-21} = Ra;
-  let Inst{20-0} = disp;
+  let Inst{20-16} = Rb;
+  let Inst{15-14} = TB;
+  let Inst{13-0} = disp;
 }
-let isBranch = 1, isTerminator = 1 in
-class BForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OperandList = (ops GPRC:$RA, target:$DISP);
 
+//3.3.2
+def target : Operand<OtherVT> {}
+
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
+class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+   : InstAlpha<opcode, asmstr, itin> {
+  let OutOperandList = (ops);
+  let InOperandList = OL;
+  bits<64> Opc; //dummy
   bits<5> Ra;
   bits<21> disp;
 
   let Inst{25-21} = Ra;
   let Inst{20-0} = disp;
 }
+}
 
 let isBranch = 1, isTerminator = 1 in
-class FBForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops F8RC:$RA, target:$DISP);
-
+  let OutOperandList = (ops);
+  let InOperandList = (ops target:$DISP);
   bits<5> Ra;
   bits<21> disp;
 
@@ -119,7 +135,8 @@ class FBForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass it
 class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RC, GPRC:$RA, GPRC:$RB);
+  let OutOperandList = (outs GPRC:$RC);
+  let InOperandList = (ins GPRC:$RA, GPRC:$RB);
 
   bits<5> Rc;
   bits<5> Ra;
@@ -137,7 +154,8 @@ class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Instr
 class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RC, GPRC:$RB);
+  let OutOperandList = (outs GPRC:$RC);
+  let InOperandList = (ins GPRC:$RB);
 
   bits<5> Rc;
   bits<5> Rb;
@@ -154,14 +172,17 @@ class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Inst
 class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, GPRC:$RTRUE, GPRC:$RCOND);
+  let OutOperandList = (outs GPRC:$RDEST);
+  let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
+  let Constraints = "$RFALSE = $RDEST";
+  let DisableEncoding = "$RFALSE";
 
   bits<5> Rc;
-  bits<5> Rb;
   bits<5> Ra;
+  bits<5> Rb;
   bits<7> Function = fun;
 
-  let isTwoAddress = 1;
+//  let isTwoAddress = 1;
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
   let Inst{15-13} = 0;
@@ -174,7 +195,8 @@ class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Inst
 class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RC, GPRC:$RA, u8imm:$L);
+  let OutOperandList = (outs GPRC:$RC);
+  let InOperandList = (ins GPRC:$RA, u8imm:$L);
 
   bits<5> Rc;
   bits<5> Ra;
@@ -191,14 +213,17 @@ class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, Inst
 class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<opcode, asmstr, itin> {
   let Pattern = pattern;
-  let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, s64imm:$RTRUE, GPRC:$RCOND);
- 
+  let OutOperandList = (outs GPRC:$RDEST);
+  let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
+  let Constraints = "$RFALSE = $RDEST";
+  let DisableEncoding = "$RFALSE";
+
   bits<5> Rc;
-  bits<8> LIT;
   bits<5> Ra;
+  bits<8> LIT;
   bits<7> Function = fun;
 
-  let isTwoAddress = 1;
+//  let isTwoAddress = 1;
   let Inst{25-21} = Ra;
   let Inst{20-13} = LIT;
   let Inst{12} = 1;
@@ -225,7 +250,8 @@ class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, Ins
 //3.3.5
 class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
     : InstAlpha<opcode, asmstr, itin> {
-  let OperandList = OL;
+  let OutOperandList = (ops);
+  let InOperandList = OL;
   bits<26> Function;
 
   let Inst{25-0} = Function;
@@ -233,9 +259,10 @@ class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
 
 
 // Pseudo instructions.
-class PseudoInstAlpha<dag OL, string nm, list<dag> pattern, InstrItinClass itin> 
+class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin> 
     : InstAlpha<0, nm, itin>  {
-  let OperandList = OL;
+  let OutOperandList = OOL;
+  let InOperandList = IOL;
   let Pattern = pattern;
 
 }