//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Andrew Lenharth and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Start the numbering where the builting ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
//These corrospond to the identical Instruction
- ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
+ CVTQT_, CVTQS_, CVTTQ_,
/// GPRelHi/GPRelLo - These represent the high and low 16-bit
/// parts of a global address respectively.
DivCall,
/// return flag operand
- RET_FLAG
+ RET_FLAG,
+
+ /// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
+ /// corresponds to the COND_BRANCH pseudo instruction.
+ /// *PRC is the input register to compare to zero,
+ /// OPC is the branch opcode to use (e.g. Alpha::BEQ),
+ /// DESTBB is the destination block to branch to, and INFLAG is
+ /// an optional input flag argument.
+ COND_BRANCH_I, COND_BRANCH_F
};
}
class AlphaTargetLowering : public TargetLowering {
int VarArgsOffset; // What is the offset to the first vaarg
int VarArgsBase; // What is the base FrameIndex
- unsigned GP; //GOT vreg
- unsigned RA; //Return Address
bool useITOF;
public:
- AlphaTargetLowering(TargetMachine &TM);
+ explicit AlphaTargetLowering(TargetMachine &TM);
+ /// getSetCCResultType - Get the SETCC result ValueType
+ virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
- bool isTailCall, SDOperand Callee, ArgListTy &Args,
- SelectionDAG &DAG);
+ LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
+ bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
+ ArgListTy &Args, SelectionDAG &DAG);
- ConstraintType getConstraintType(char ConstraintLetter) const;
+ ConstraintType getConstraintType(const std::string &Constraint) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
- void restoreGP(MachineBasicBlock* BB);
- void restoreRA(MachineBasicBlock* BB);
- unsigned getVRegGP() { return GP; }
- unsigned getVRegRA() { return RA; }
bool hasITOF() { return useITOF; }
+
+ MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
+ MachineBasicBlock *BB);
};
}