Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's

[oota-llvm.git] / lib / Target / Alpha / AlphaISelLowering.h

diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 0c1db073ee9afdbc77aa68d244b7c4a0b660c14a..8738d02f4d3d01bb84b2b2e0791708b2618c16ca 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Andrew Lenharth and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -27,7 +27,7 @@ namespace llvm {
       // Start the numbering where the builting ops and target ops leave off.
       FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
       //These corrospond to the identical Instruction
-      ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
+      CVTQT_, CVTQS_, CVTTQ_,
 
       /// GPRelHi/GPRelLo - These represent the high and low 16-bit
       /// parts of a global address respectively.
@@ -64,8 +64,11 @@ namespace llvm {
     int VarArgsBase;    // What is the base FrameIndex
     bool useITOF;
   public:
-    AlphaTargetLowering(TargetMachine &TM);
+    explicit AlphaTargetLowering(TargetMachine &TM);
     
+    /// getSetCCResultType - Get the SETCC result ValueType
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
@@ -77,17 +80,20 @@ namespace llvm {
     /// LowerCallTo - This hook lowers an abstract call to a function into an
     /// actual call.
     virtual std::pair<SDOperand, SDOperand>
-    LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
-                bool isTailCall, SDOperand Callee, ArgListTy &Args,
-                SelectionDAG &DAG);
+    LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
+                bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 
+                ArgListTy &Args, SelectionDAG &DAG);
 
-    ConstraintType getConstraintType(char ConstraintLetter) const;
+    ConstraintType getConstraintType(const std::string &Constraint) const;
 
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         MVT::ValueType VT) const;
 
     bool hasITOF() { return useITOF; }
+
+    MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
+                                                   MachineBasicBlock *BB);
   };
 }