#include "llvm/Support/MathExtras.h"
#include <algorithm>
#include <iostream>
+#include <queue>
#include <set>
using namespace llvm;
return x - get_ldah16(x) * IMM_MULT;
}
+ /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
+ /// instruction (if not, return 0). Note that this code accepts partial
+ /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
+ /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
+ /// in checking mode. If LHS is null, we assume that the mask has already
+ /// been validated before.
+ uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
+ uint64_t BitsToCheck = 0;
+ unsigned Result = 0;
+ for (unsigned i = 0; i != 8; ++i) {
+ if (((Constant >> 8*i) & 0xFF) == 0) {
+ // nothing to do.
+ } else {
+ Result |= 1 << i;
+ if (((Constant >> 8*i) & 0xFF) == 0xFF) {
+ // If the entire byte is set, zapnot the byte.
+ } else if (LHS.Val == 0) {
+ // Otherwise, if the mask was previously validated, we know its okay
+ // to zapnot this entire byte even though all the bits aren't set.
+ } else {
+ // Otherwise we don't know that the it's okay to zapnot this entire
+ // byte. Only do this iff we can prove that the missing bits are
+ // already null, so the bytezap doesn't need to really null them.
+ BitsToCheck |= ~Constant & (0xFF << 8*i);
+ }
+ }
+ }
+
+ // If there are missing bits in a byte (for example, X & 0xEF00), check to
+ // see if the missing bits (0x1000) are already known zero if not, the zap
+ // isn't okay to do, as it won't clear all the required bits.
+ if (BitsToCheck &&
+ !getTargetLowering().MaskedValueIsZero(LHS, BitsToCheck))
+ return 0;
+
+ return Result;
+ }
+
static uint64_t get_zapImm(uint64_t x) {
- unsigned int build = 0;
- for(int i = 0; i < 8; ++i)
- {
- if ((x & 0x00FF) == 0x00FF)
- build |= 1 << i;
- else if ((x & 0x00FF) != 0)
- { build = 0; break; }
- x >>= 8;
- }
+ unsigned build = 0;
+ for(int i = 0; i != 8; ++i) {
+ if ((x & 0x00FF) == 0x00FF)
+ build |= 1 << i;
+ else if ((x & 0x00FF) != 0)
+ return 0;
+ x >>= 8;
+ }
return build;
}
-
+
+
static uint64_t getNearPower2(uint64_t x) {
if (!x) return 0;
unsigned at = CountLeadingZeros_64(x);
return comphigh;
}
+ static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
+ uint64_t y = getNearPower2(x);
+ if (swap)
+ return (y - x) == r;
+ else
+ return (x - y) == r;
+ }
+
static bool isFPZ(SDOperand N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
public:
AlphaDAGToDAGISel(TargetMachine &TM)
- : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
+ : SelectionDAGISel(AlphaLowering),
+ AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
{}
/// getI64Imm - Return a target constant with the specified value, of type
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- void Select(SDOperand &Result, SDOperand Op);
+ SDNode *Select(SDOperand Op);
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
return "Alpha DAG->DAG Pattern Instruction Selection";
}
+ /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+ /// inline asm expressions.
+ virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ char ConstraintCode,
+ std::vector<SDOperand> &OutOps,
+ SelectionDAG &DAG) {
+ SDOperand Op0;
+ switch (ConstraintCode) {
+ default: return true;
+ case 'm': // memory
+ Op0 = Op;
+ AddToISelQueue(Op0);
+ break;
+ }
+
+ OutOps.push_back(Op0);
+ return false;
+ }
+
// Include the pieces autogenerated from the target description.
#include "AlphaGenDAGISel.inc"
private:
SDOperand getGlobalBaseReg();
SDOperand getGlobalRetAddr();
- SDOperand SelectCALL(SDOperand Op);
+ void SelectCALL(SDOperand Op);
};
}
/// GOT address into a register.
///
SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
+ MachineFunction* MF = BB->getParent();
+ unsigned GP = 0;
+ for(MachineFunction::livein_iterator ii = MF->livein_begin(),
+ ee = MF->livein_end(); ii != ee; ++ii)
+ if (ii->first == Alpha::R29) {
+ GP = ii->second;
+ break;
+ }
+ assert(GP && "GOT PTR not in liveins");
return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
- AlphaLowering.getVRegGP(),
- MVT::i64);
+ GP, MVT::i64);
}
/// getRASaveReg - Grab the return address
///
SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
+ MachineFunction* MF = BB->getParent();
+ unsigned RA = 0;
+ for(MachineFunction::livein_iterator ii = MF->livein_begin(),
+ ee = MF->livein_end(); ii != ee; ++ii)
+ if (ii->first == Alpha::R26) {
+ RA = ii->second;
+ break;
+ }
+ assert(RA && "RA PTR not in liveins");
return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
- AlphaLowering.getVRegRA(),
- MVT::i64);
+ RA, MVT::i64);
}
/// InstructionSelectBasicBlock - This callback is invoked by
// Select target instructions for the DAG.
DAG.setRoot(SelectRoot(DAG.getRoot()));
- assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
- CodeGenMap.clear();
- HandleMap.clear();
- ReplaceMap.clear();
DAG.RemoveDeadNodes();
// Emit machine code to BB.
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
N->getOpcode() < AlphaISD::FIRST_NUMBER) {
- Result = Op;
- return; // Already selected.
- }
-
- // If this has already been converted, use it.
- std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) {
- Result = CGMI->second;
- return;
+ return NULL; // Already selected.
}
switch (N->getOpcode()) {
default: break;
case AlphaISD::CALL:
- Result = SelectCALL(Op);
- return;
+ SelectCALL(Op);
+ return NULL;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i32),
- getI64Imm(0));
- return;
+ return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ getI64Imm(0));
+ }
+ case ISD::GLOBAL_OFFSET_TABLE: {
+ SDOperand Result = getGlobalBaseReg();
+ ReplaceUses(Op, Result);
+ return NULL;
+ }
+ case AlphaISD::GlobalRetAddr: {
+ SDOperand Result = getGlobalRetAddr();
+ ReplaceUses(Op, Result);
+ return NULL;
}
- case AlphaISD::GlobalBaseReg:
- Result = getGlobalBaseReg();
- return;
- case AlphaISD::GlobalRetAddr:
- Result = getGlobalRetAddr();
- return;
case AlphaISD::DivCall: {
SDOperand Chain = CurDAG->getEntryNode();
- SDOperand N0, N1, N2;
- Select(N0, Op.getOperand(0));
- Select(N1, Op.getOperand(1));
- Select(N2, Op.getOperand(2));
+ SDOperand N0 = Op.getOperand(0);
+ SDOperand N1 = Op.getOperand(1);
+ SDOperand N2 = Op.getOperand(2);
+ AddToISelQueue(N0);
+ AddToISelQueue(N1);
+ AddToISelQueue(N2);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
SDOperand(0,0));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
Chain, Chain.getValue(1));
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
SDOperand(CNode, 1));
- Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
- return;
+ return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
- SDOperand Chain;
- Select(Chain, N->getOperand(0)); //Select chain
- Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
- return;
+ SDOperand Chain = N->getOperand(0);
+ AddToISelQueue(Chain); //Select chain
+ return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
+ Chain);
}
case ISD::Constant: {
uint64_t uval = cast<ConstantSDNode>(N)->getValue();
if (uval == 0) {
- Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
- MVT::i64);
- return;
+ SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ Alpha::R31, MVT::i64);
+ ReplaceUses(Op, Result);
+ return NULL;
}
int64_t val = (int64_t)uval;
break; //(zext (LDAH (LDA)))
//Else use the constant pool
MachineConstantPool *CP = BB->getParent()->getConstantPool();
- ConstantUInt *C =
- ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
+ ConstantInt *C = ConstantInt::get(Type::ULongTy, uval);
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg());
- Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
- CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
- return;
+ return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
+ CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
bool isDouble = N->getValueType(0) == MVT::f64;
MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
if (CN->isExactlyValue(+0.0)) {
- Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
- T, CurDAG->getRegister(Alpha::F31, T),
- CurDAG->getRegister(Alpha::F31, T));
- return;
+ return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
+ T, CurDAG->getRegister(Alpha::F31, T),
+ CurDAG->getRegister(Alpha::F31, T));
} else if ( CN->isExactlyValue(-0.0)) {
- Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
- T, CurDAG->getRegister(Alpha::F31, T),
- CurDAG->getRegister(Alpha::F31, T));
- return;
+ return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
+ T, CurDAG->getRegister(Alpha::F31, T),
+ CurDAG->getRegister(Alpha::F31, T));
} else {
abort();
}
bool rev = false;
bool isNE = false;
switch(CC) {
- default: N->dump(); assert(0 && "Unknown FP comparison!");
+ default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break;
case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: Opc = Alpha::CMPTLT; break;
case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: Opc = Alpha::CMPTLE; break;
case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: Opc = Alpha::CMPTLE; rev = true; break;
case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: Opc = Alpha::CMPTEQ; isNE = true; break;
};
- SDOperand tmp1, tmp2;
- Select(tmp1, N->getOperand(0));
- Select(tmp2, N->getOperand(1));
+ SDOperand tmp1 = N->getOperand(0);
+ SDOperand tmp2 = N->getOperand(1);
+ AddToISelQueue(tmp1);
+ AddToISelQueue(tmp2);
SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64,
rev?tmp2:tmp1,
rev?tmp1:tmp2);
CurDAG->getRegister(Alpha::R31, MVT::i64),
ST), 0);
}
- Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
- CurDAG->getRegister(Alpha::R31, MVT::i64),
- LD), 0);
- return;
+ return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
+ LD);
}
break;
// so that things like this can be caught in fall though code
//move int to fp
bool isDouble = N->getValueType(0) == MVT::f64;
- SDOperand LD, cond, TV, FV;
- Select(cond, N->getOperand(0));
- Select(TV, N->getOperand(1));
- Select(FV, N->getOperand(2));
+ SDOperand LD;
+ SDOperand cond = N->getOperand(0);
+ SDOperand TV = N->getOperand(1);
+ SDOperand FV = N->getOperand(2);
+ AddToISelQueue(cond);
+ AddToISelQueue(TV);
+ AddToISelQueue(FV);
if (AlphaLowering.hasITOF()) {
LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
CurDAG->getRegister(Alpha::R31, MVT::i64),
ST), 0);
}
- Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
- MVT::f64, FV, TV, LD), 0);
- return;
+ return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
+ MVT::f64, FV, TV, LD);
}
break;
{
uint64_t sval = SC->getValue();
uint64_t mval = MC->getValue();
- if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
+ // If the result is a zap, let the autogened stuff handle it.
+ if (get_zapImm(N->getOperand(0), mval))
break;
- // given mask X, and shift S, we want to see if there is any zap in the mask
- // if we play around with the botton S bits
+ // given mask X, and shift S, we want to see if there is any zap in the
+ // mask if we play around with the botton S bits
uint64_t dontcare = (~0ULL) >> (64 - sval);
uint64_t mask = mval << sval;
mask = mask | dontcare;
if (get_zapImm(mask)) {
- SDOperand Src;
- Select(Src, N->getOperand(0).getOperand(0));
+ AddToISelQueue(N->getOperand(0).getOperand(0));
SDOperand Z =
- SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src,
+ SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
+ N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
- Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
- getI64Imm(sval)), 0);
- return;
+ return CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z,
+ getI64Imm(sval));
}
}
break;
}
- SelectCode(Result, Op);
+ return SelectCode(Op);
}
-SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
+void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
//TODO: add flag stuff to prevent nondeturministic breakage!
SDNode *N = Op.Val;
- SDOperand Chain;
+ SDOperand Chain = N->getOperand(0);
SDOperand Addr = N->getOperand(1);
SDOperand InFlag(0,0); // Null incoming flag value.
- Select(Chain, N->getOperand(0));
+ AddToISelQueue(Chain);
std::vector<SDOperand> CallOperands;
std::vector<MVT::ValueType> TypeOperands;
//grab the arguments
for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
- SDOperand Tmp;
TypeOperands.push_back(N->getOperand(i).getValueType());
- Select(Tmp, N->getOperand(i));
- CallOperands.push_back(Tmp);
+ AddToISelQueue(N->getOperand(i));
+ CallOperands.push_back(N->getOperand(i));
}
int count = N->getNumOperands() - 2;
Opc = Alpha::STT;
} else
assert(0 && "Unknown operand");
- Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
- getI64Imm((i - 6) * 8),
- CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
- Chain), 0);
+
+ SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
+ CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
+ Chain };
+ Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
}
for (int i = 0; i < std::min(6, count); ++i) {
if (MVT::isInteger(TypeOperands[i])) {
Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
Addr.getOperand(0), Chain, InFlag), 0);
} else {
- Select(Addr, Addr);
+ AddToISelQueue(Addr);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
CallResults.push_back(Chain);
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
- CodeGenMap[Op.getValue(i)] = CallResults[i];
- return CallResults[Op.ResNo];
+ ReplaceUses(Op.getValue(i), CallResults[i]);
}
projects / oota-llvm.git / blobdiff