[ARM64] Add a big endian version of the ARM64 target machine, and update all users.

[oota-llvm.git] / lib / Target / ARM64 / ARM64TargetMachine.cpp

diff --git a/lib/Target/ARM64/ARM64TargetMachine.cpp b/lib/Target/ARM64/ARM64TargetMachine.cpp
index 8070ce0d8b2a2bb5f1617a012defe60e34da70b0..7e3228f0230c4dac0f0cef77cf63a305a63d128f 100644 (file)
--- a/lib/Target/ARM64/ARM64TargetMachine.cpp
+++ b/lib/Target/ARM64/ARM64TargetMachine.cpp
@@ -49,7 +49,8 @@ EnableDeadRegisterElimination("arm64-dead-def-elimination", cl::Hidden,
 
 extern "C" void LLVMInitializeARM64Target() {
   // Register the target.
-  RegisterTargetMachine<ARM64TargetMachine> X(TheARM64Target);
+  RegisterTargetMachine<ARM64leTargetMachine> X(TheARM64leTarget);
+  RegisterTargetMachine<ARM64beTargetMachine> Y(TheARM64beTarget);
 }
 
 /// TargetMachine ctor - Create an ARM64 architecture model.
@@ -58,16 +59,40 @@ ARM64TargetMachine::ARM64TargetMachine(const Target &T, StringRef TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
-                                       CodeGenOpt::Level OL)
+                                       CodeGenOpt::Level OL,
+                                       bool LittleEndian)
     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-      Subtarget(TT, CPU, FS),
-      DL(Subtarget.isTargetMachO() ? "e-m:o-i64:64-i128:128-n32:64-S128"
-                                   : "e-m:e-i64:64-i128:128-n32:64-S128"),
+      Subtarget(TT, CPU, FS, LittleEndian),
+      // This nested ternary is horrible, but DL needs to be properly initialized
+      // before TLInfo is constructed.
+      DL(Subtarget.isTargetMachO() ?
+         "e-m:o-i64:64-i128:128-n32:64-S128" :
+         (LittleEndian ?
+          "e-m:e-i64:64-i128:128-n32:64-S128" :
+          "E-m:e-i64:64-i128:128-n32:64-S128")),
       InstrInfo(Subtarget), TLInfo(*this), FrameLowering(*this, Subtarget),
       TSInfo(*this) {
   initAsmInfo();
 }
 
+void ARM64leTargetMachine::anchor() { }
+
+ARM64leTargetMachine::
+ARM64leTargetMachine(const Target &T, StringRef TT,
+                       StringRef CPU, StringRef FS, const TargetOptions &Options,
+                       Reloc::Model RM, CodeModel::Model CM,
+                       CodeGenOpt::Level OL)
+  : ARM64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+
+void ARM64beTargetMachine::anchor() { }
+
+ARM64beTargetMachine::
+ARM64beTargetMachine(const Target &T, StringRef TT,
+                       StringRef CPU, StringRef FS, const TargetOptions &Options,
+                       Reloc::Model RM, CodeModel::Model CM,
+                       CodeGenOpt::Level OL)
+  : ARM64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+
 namespace {
 /// ARM64 Code Generator Pass Configuration Options.
 class ARM64PassConfig : public TargetPassConfig {