#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCContext.h"
-#include "llvm/Target/TargetRegistry.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
// Pull DecodeStatus and its enum values into the global namespace.
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
- uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
-
static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
uint8_t bytes[4];
// We want to read exactly 4 bytes of data.
- if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
+ if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
+ Size = 0;
return Fail;
+ }
// Encoded as a small-endian 32-bit word in the stream.
uint32_t insn = (bytes[3] << 24) |
MI.clear();
+ Size = 0;
return Fail;
}
unsigned CC;
if (!ITBlock.empty()) {
CC = ITBlock.back();
+ if (CC == 0xF)
+ CC = ARMCC::AL;
ITBlock.pop_back();
} else
CC = ARMCC::AL;
const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
MCInst::iterator I = MI.begin();
- for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
+ unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+ for (unsigned i = 0; i < NumOps; ++i, ++I) {
if (OpInfo[i].isPredicate() ) {
I->setImm(CC);
++I;
uint8_t bytes[4];
// We want to read exactly 2 bytes of data.
- if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
+ if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
+ Size = 0;
return Fail;
+ }
uint16_t insn16 = (bytes[1] << 8) | bytes[0];
DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
}
// We want to read exactly 4 bytes of data.
- if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
+ if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
+ Size = 0;
return Fail;
+ }
uint32_t insn32 = (bytes[3] << 8) |
(bytes[2] << 0) |
}
}
+ Size = 0;
return Fail;
}
return Success;
}
-static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
- uint64_t Address, const void *Decoder) {
- Val <<= 2;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
- return Success;
-}
-
static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
case ARM::LDR_POST_REG:
case ARM::LDRB_POST_IMM:
case ARM::LDRB_POST_REG:
- case ARM::LDR_PRE:
- case ARM::LDRB_PRE:
case ARM::LDRBT_POST_REG:
case ARM::LDRBT_POST_IMM:
case ARM::LDRT_POST_REG:
return S;
}
+static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned imod = fieldFromInstruction32(Insn, 9, 2);
+ unsigned M = fieldFromInstruction32(Insn, 8, 1);
+ unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
+ unsigned mode = fieldFromInstruction32(Insn, 0, 5);
+
+ DecodeStatus S = Success;
+
+ // imod == '01' --> UNPREDICTABLE
+ // NOTE: Even though this is technically UNPREDICTABLE, we choose to
+ // return failure here. The '01' imod value is unprintable, so there's
+ // nothing useful we could do even if we returned UNPREDICTABLE.
+
+ if (imod == 1) CHECK(S, Fail);
+
+ if (imod && M) {
+ Inst.setOpcode(ARM::t2CPS3p);
+ Inst.addOperand(MCOperand::CreateImm(imod));
+ Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::CreateImm(mode));
+ } else if (imod && !M) {
+ Inst.setOpcode(ARM::t2CPS2p);
+ Inst.addOperand(MCOperand::CreateImm(imod));
+ Inst.addOperand(MCOperand::CreateImm(iflags));
+ if (mode) CHECK(S, Unpredictable);
+ } else if (!imod && M) {
+ Inst.setOpcode(ARM::t2CPS1p);
+ Inst.addOperand(MCOperand::CreateImm(mode));
+ if (iflags) CHECK(S, Unpredictable);
+ } else {
+ // imod == '00' && M == '0' --> UNPREDICTABLE
+ Inst.setOpcode(ARM::t2CPS1p);
+ Inst.addOperand(MCOperand::CreateImm(mode));
+ CHECK(S, Unpredictable);
+ }
+
+ return S;
+}
+
+
static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
- if (Inst.getOpcode() == ARM::tADR)
- Inst.addOperand(MCOperand::CreateReg(ARM::PC));
- else if (Inst.getOpcode() == ARM::tADDrSPi)
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- else
- return Fail;
+ switch(Inst.getOpcode()) {
+ default:
+ return Fail;
+ case ARM::tADR:
+ break; // tADR does not explicitly represent the PC as an operand.
+ case ARM::tADDrSPi:
+ Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ break;
+ }
Inst.addOperand(MCOperand::CreateImm(imm));
return S;
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
- if (Inst.getOpcode() != ARM::t2PLDs) {
- unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ switch (Inst.getOpcode()) {
+ case ARM::t2PLDs:
+ case ARM::t2PLDWs:
+ case ARM::t2PLIs:
+ break;
+ default: {
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ }
}
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
+ Inst.addOperand(MCOperand::CreateReg(ARM::SP));
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
return S;
}
+static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = Success;
+
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned imm = fieldFromInstruction32(Insn, 0, 12);
+ imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
+ imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+
+ if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
+
+ CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
+ CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+
+ return S;
+}
+
+static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = Success;
+
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned imm = fieldFromInstruction32(Insn, 0, 12);
+ imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
+ imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+ unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+
+ if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
+ if (Rm == 0xF) CHECK(S, Unpredictable);
+
+ CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
+ CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+
+ return S;
+}
+
+
static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
return S;
}
+
+static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = Success;
+ if (Cond == 0xF) {
+ Cond = 0xE;
+ CHECK(S, Unpredictable);
+ }
+
+ Inst.addOperand(MCOperand::CreateImm(Cond));
+ return S;
+}
+
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = Success;
+ if (Mask == 0) {
+ Mask = 0x8;
+ CHECK(S, Unpredictable);
+ }
+ Inst.addOperand(MCOperand::CreateImm(Mask));
+ return S;
+}
+
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