if (I == MI.end()) break;
if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && OpInfo[i-1].isPredicate()) continue;
- MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
return;
}
}
- MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
}
// Most Thumb instructions don't have explicit predicates in the
for (unsigned i = 0; i < NumOps; ++i, ++I) {
if (I == MI.end()) break;
if (OpInfo[i].isPredicate()) {
- I = MI.insert(I, MCOperand::CreateImm(CC));
+ I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
- MI.insert(I, MCOperand::CreateReg(0));
+ MI.insert(I, MCOperand::createReg(0));
else
- MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
}
- I = MI.insert(I, MCOperand::CreateImm(CC));
+ I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
- MI.insert(I, MCOperand::CreateReg(0));
+ MI.insert(I, MCOperand::createReg(0));
else
- MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+ MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
if (RegNo == 15)
{
- Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
+ Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success;
}
S = MCDisassembler::SoftFail;
unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
- Inst.addOperand(MCOperand::CreateReg(RegisterPair));
+ Inst.addOperand(MCOperand::createReg(RegisterPair));
return S;
}
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
unsigned Register = SPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
unsigned Register = DPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
RegNo >>= 1;
unsigned Register = QPRDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
unsigned Register = DPairDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
unsigned Register = DPairSpacedDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Register));
+ Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
// AL predicate is not allowed on Thumb1 branches.
if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
if (Val == ARMCC::AL) {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
} else
- Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+ Inst.addOperand(MCOperand::createReg(ARM::CPSR));
return MCDisassembler::Success;
}
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val)
- Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+ Inst.addOperand(MCOperand::createReg(ARM::CPSR));
else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
return MCDisassembler::Success;
}
Shift = ARM_AM::rrx;
unsigned Op = Shift | (imm << 3);
- Inst.addOperand(MCOperand::CreateImm(Op));
+ Inst.addOperand(MCOperand::createImm(Op));
return S;
}
break;
}
- Inst.addOperand(MCOperand::CreateImm(Shift));
+ Inst.addOperand(MCOperand::createImm(Shift));
return S;
}
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
uint32_t lsb_mask = (1U << lsb) - 1;
- Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
+ Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
return S;
}
if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(coproc));
- Inst.addOperand(MCOperand::CreateImm(CRd));
+ Inst.addOperand(MCOperand::createImm(coproc));
+ Inst.addOperand(MCOperand::createImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
case ARM::STC_PRE:
case ARM::STCL_PRE:
imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
case ARM::t2LDC2_POST:
case ARM::t2LDC2L_POST:
default:
// The 'option' variant doesn't encode 'U' in the immediate since
// the immediate is unsigned [0,255].
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
}
Opc = ARM_AM::rrx;
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
} else {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
- Inst.addOperand(MCOperand::CreateImm(tmp));
+ Inst.addOperand(MCOperand::createImm(tmp));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
else
shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
- Inst.addOperand(MCOperand::CreateImm(shift));
+ Inst.addOperand(MCOperand::createImm(shift));
return S;
}
return MCDisassembler::Fail;
if (type) {
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
+ Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
} else {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(U));
+ Inst.addOperand(MCOperand::createImm(U));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
break;
}
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
return MCDisassembler::Fail;
Inst.addOperand(
- MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
+ MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
return S;
}
if (imod && M) {
Inst.setOpcode(ARM::CPS3p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
+ Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::CPS2p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
S = MCDisassembler::SoftFail;
}
if (imod && M) {
Inst.setOpcode(ARM::t2CPS3p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
+ Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::t2CPS2p);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(iflags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::t2CPS1p);
- Inst.addOperand(MCOperand::CreateImm(mode));
+ Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> this is a HINT instruction
// HINT are defined only for immediate in [0..4]
if(imm > 4) return MCDisassembler::Fail;
Inst.setOpcode(ARM::t2HINT);
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
}
return S;
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
S = MCDisassembler::SoftFail;
Inst.setOpcode(ARM::SETPAN);
- Inst.addOperand(MCOperand::CreateImm(Imm));
+ Inst.addOperand(MCOperand::createImm(Imm));
return S;
}
if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
if (Rn == 15)
tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
return MCDisassembler::Fail;
if (U)
- Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
+ Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
else
- Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
+ Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
return S;
}
int imm32 = SignExtend32<25>(tmp << 1);
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return Status;
}
imm |= fieldFromInstruction(Insn, 24, 1) << 1;
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
return S;
}
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!align)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else
- Inst.addOperand(MCOperand::CreateImm(4 << align));
+ Inst.addOperand(MCOperand::createImm(4 << align));
return S;
}
case ARM::VLD2b8wb_register:
case ARM::VLD2b16wb_register:
case ARM::VLD2b32wb_register:
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD:
//
// The fixed offset encodes as Rm == 0xd, so we check for that.
if (Rm == 0xd) {
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
break;
}
// Fall through to handle the register offset variant.
case ARM::VST2b32wb_register:
if (Rm == 0xF)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD:
switch (Inst.getOpcode()) {
default:
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
// variant encodes Rm == 0xf. Anything else is a register offset post-
}
if (Rm != 0xF)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xD && Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) {
case ARM::VORRiv4i16:
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(8 << size));
+ Inst.addOperand(MCOperand::createImm(8 << size));
return S;
}
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(8 - Val));
+ Inst.addOperand(MCOperand::createImm(8 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(16 - Val));
+ Inst.addOperand(MCOperand::createImm(16 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(32 - Val));
+ Inst.addOperand(MCOperand::createImm(32 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(64 - Val));
+ Inst.addOperand(MCOperand::createImm(64 - Val));
return MCDisassembler::Success;
}
case ARM::tADR:
break; // tADR does not explicitly represent the PC as an operand.
case ARM::tADDrSPi:
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
break;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
return MCDisassembler::Success;
}
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
return MCDisassembler::Success;
}
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(Val << 1));
+ Inst.addOperand(MCOperand::createImm(Val << 1));
return MCDisassembler::Success;
}
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
uint64_t Address, const void *Decoder) {
unsigned imm = Val << 2;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
return MCDisassembler::Success;
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
else
imm = -imm;
}
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0)
- Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
+ Inst.addOperand(MCOperand::createImm(INT32_MIN));
else {
int imm = Val & 0xFF;
if (!(Val & 0x100)) imm *= -1;
- Inst.addOperand(MCOperand::CreateImm(imm * 4));
+ Inst.addOperand(MCOperand::createImm(imm * 4));
}
return MCDisassembler::Success;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
imm = INT32_MIN;
else if (!(Val & 0x100))
imm *= -1;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
return S;
}
uint64_t Address, const void *Decoder) {
unsigned imm = fieldFromInstruction(Insn, 0, 7);
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4);
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
+ Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
unsigned flags = fieldFromInstruction(Insn, 0, 3);
- Inst.addOperand(MCOperand::CreateImm(imod));
- Inst.addOperand(MCOperand::CreateImm(flags));
+ Inst.addOperand(MCOperand::createImm(imod));
+ Inst.addOperand(MCOperand::createImm(flags));
return MCDisassembler::Success;
}
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(add));
+ Inst.addOperand(MCOperand::createImm(add));
return S;
}
if (!tryAddingSymbolicOperand(Address,
(Address & ~2u) + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
unsigned imm = fieldFromInstruction(Val, 0, 8);
switch (byte) {
case 0:
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
break;
case 1:
- Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
+ Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
break;
case 2:
- Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
break;
case 3:
- Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
+ Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
(imm << 8) | imm));
break;
}
unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
unsigned rot = fieldFromInstruction(Val, 7, 5);
unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
- Inst.addOperand(MCOperand::CreateImm(imm));
+ Inst.addOperand(MCOperand::createImm(imm));
}
return MCDisassembler::Success;
uint64_t Address, const void *Decoder){
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
true, 2, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
return MCDisassembler::Success;
}
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
- Inst.addOperand(MCOperand::CreateImm(imm32));
+ Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
if (Val & ~0xf)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
if (Val & ~0xf)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
if (Val == 0)
return MCDisassembler::Fail;
}
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
return MCDisassembler::SoftFail;
}
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(align));
+ Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(index));
+ Inst.addOperand(MCOperand::createImm(index));
return S;
}
if (mask == 0x0)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(pred));
- Inst.addOperand(MCOperand::CreateImm(mask));
+ Inst.addOperand(MCOperand::createImm(pred));
+ Inst.addOperand(MCOperand::createImm(mask));
return S;
}
Val |= fieldFromInstruction(Insn, 12, 3) << 8;
Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Val |= sign1 << 12;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
return MCDisassembler::Success;
}
// Shift of "asr #32" is not allowed in Thumb2 mode.
if (Val == 0x20) S = MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(Val));
+ Inst.addOperand(MCOperand::createImm(Val));
return S;
}
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(64 - imm));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(64 - imm));
+ Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
if (Rt == Rt2)
S = MCDisassembler::SoftFail;
- Inst.addOperand(MCOperand::CreateImm(cop));
- Inst.addOperand(MCOperand::CreateImm(opc1));
+ Inst.addOperand(MCOperand::createImm(cop));
+ Inst.addOperand(MCOperand::createImm(opc1));
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateImm(CRm));
+ Inst.addOperand(MCOperand::createImm(CRm));
return S;
}