#define DEBUG_TYPE "arm-disassembler"
-#include "ARMDisassembler.h"
#include "ARM.h"
-#include "ARMRegisterInfo.h"
+#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
+#include "MCTargetDesc/ARMMCExpr.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/MC/EDInstInfo.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDisassembler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
-// Pull DecodeStatus and its enum values into the global namespace.
-typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
-#define Success llvm::MCDisassembler::Success
-#define Unpredictable llvm::MCDisassembler::SoftFail
-#define Fail llvm::MCDisassembler::Fail
+using namespace llvm;
+
+typedef MCDisassembler::DecodeStatus DecodeStatus;
+
+namespace {
+/// ARMDisassembler - ARM disassembler for all ARM platforms.
+class ARMDisassembler : public MCDisassembler {
+public:
+ /// Constructor - Initializes the disassembler.
+ ///
+ ARMDisassembler(const MCSubtargetInfo &STI) :
+ MCDisassembler(STI) {
+ }
+
+ ~ARMDisassembler() {
+ }
+
+ /// getInstruction - See MCDisassembler.
+ DecodeStatus getInstruction(MCInst &instr,
+ uint64_t &size,
+ const MemoryObject ®ion,
+ uint64_t address,
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
+
+ /// getEDInfo - See MCDisassembler.
+ EDInstInfo *getEDInfo() const;
+private:
+};
+
+/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
+class ThumbDisassembler : public MCDisassembler {
+public:
+ /// Constructor - Initializes the disassembler.
+ ///
+ ThumbDisassembler(const MCSubtargetInfo &STI) :
+ MCDisassembler(STI) {
+ }
+
+ ~ThumbDisassembler() {
+ }
+
+ /// getInstruction - See MCDisassembler.
+ DecodeStatus getInstruction(MCInst &instr,
+ uint64_t &size,
+ const MemoryObject ®ion,
+ uint64_t address,
+ raw_ostream &vStream,
+ raw_ostream &cStream) const;
+
+ /// getEDInfo - See MCDisassembler.
+ EDInstInfo *getEDInfo() const;
+private:
+ mutable std::vector<unsigned> ITBlock;
+ DecodeStatus AddThumbPredicate(MCInst&) const;
+ void UpdateThumbVFPPredicate(MCInst&) const;
+};
+}
+
+static bool Check(DecodeStatus &Out, DecodeStatus In) {
+ switch (In) {
+ case MCDisassembler::Success:
+ // Out stays the same.
+ return true;
+ case MCDisassembler::SoftFail:
+ Out = In;
+ return true;
+ case MCDisassembler::Fail:
+ Out = In;
+ return false;
+ }
+ return false;
+}
-// Helper macro to perform setwise reduction of the current running status
-// and another status, and return if the new status is Fail.
-#define CHECK(S,X) do { \
- S = (DecodeStatus) ((int)S & (X)); \
- if (S == Fail) return Fail; \
- } while(0)
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
unsigned Insn,
uint64_t Adddress,
const void *Decoder);
+static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
- uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
- uint64_t Address, const void *Decoder);
static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
+
+
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
#include "ARMGenEDInfo.inc"
-using namespace llvm;
-
-static MCDisassembler *createARMDisassembler(const Target &T) {
- return new ARMDisassembler;
+static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
+ return new ARMDisassembler(STI);
}
-static MCDisassembler *createThumbDisassembler(const Target &T) {
- return new ThumbDisassembler;
+static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
+ return new ThumbDisassembler(STI);
}
EDInstInfo *ARMDisassembler::getEDInfo() const {
DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
- raw_ostream &os) const {
+ raw_ostream &os,
+ raw_ostream &cs) const {
+ CommentStream = &cs;
+
uint8_t bytes[4];
+ assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
+ "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
+
// We want to read exactly 4 bytes of data.
if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
Size = 0;
- return Fail;
+ return MCDisassembler::Fail;
}
// Encoded as a small-endian 32-bit word in the stream.
(bytes[0] << 0);
// Calling the auto-generated decoder function.
- DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
- if (result != Fail) {
- Size = 4;
- return result;
- }
-
- // Instructions that are shared between ARM and Thumb modes.
- // FIXME: This shouldn't really exist. It's an artifact of the
- // fact that we fail to encode a few instructions properly for Thumb.
- MI.clear();
- result = decodeCommonInstruction32(MI, insn, Address, this);
- if (result != Fail) {
+ DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
return result;
}
// VFP and NEON instructions, similarly, are shared between ARM
// and Thumb modes.
MI.clear();
- result = decodeVFPInstruction32(MI, insn, Address, this);
- if (result != Fail) {
+ result = decodeVFPInstruction32(MI, insn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
return result;
}
MI.clear();
- result = decodeNEONDataInstruction32(MI, insn, Address, this);
- if (result != Fail) {
+ result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
// Add a fake predicate operand, because we share these instruction
// definitions with Thumb2 where these instructions are predicable.
- if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
+ if (!DecodePredicateOperand(MI, 0xE, Address, this))
+ return MCDisassembler::Fail;
return result;
}
MI.clear();
- result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
- if (result != Fail) {
+ result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
// Add a fake predicate operand, because we share these instruction
// definitions with Thumb2 where these instructions are predicable.
- if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
+ if (!DecodePredicateOperand(MI, 0xE, Address, this))
+ return MCDisassembler::Fail;
return result;
}
MI.clear();
- result = decodeNEONDupInstruction32(MI, insn, Address, this);
- if (result != Fail) {
+ result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
// Add a fake predicate operand, because we share these instruction
// definitions with Thumb2 where these instructions are predicable.
- if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
+ if (!DecodePredicateOperand(MI, 0xE, Address, this))
+ return MCDisassembler::Fail;
return result;
}
MI.clear();
Size = 0;
- return Fail;
+ return MCDisassembler::Fail;
}
namespace llvm {
-extern MCInstrDesc ARMInsts[];
+extern const MCInstrDesc ARMInsts[];
+}
+
+/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
+/// immediate Value in the MCInst. The immediate Value has had any PC
+/// adjustment made by the caller. If the instruction is a branch instruction
+/// then isBranch is true, else false. If the getOpInfo() function was set as
+/// part of the setupForSymbolicDisassembly() call then that function is called
+/// to get any symbolic information at the Address for this instruction. If
+/// that returns non-zero then the symbolic information it returns is used to
+/// create an MCExpr and that is added as an operand to the MCInst. If
+/// getOpInfo() returns zero and isBranch is true then a symbol look up for
+/// Value is done and if a symbol is found an MCExpr is created with that, else
+/// an MCExpr with Value is created. This function returns true if it adds an
+/// operand to the MCInst and false otherwise.
+static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
+ bool isBranch, uint64_t InstSize,
+ MCInst &MI, const void *Decoder) {
+ const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
+ LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
+ if (!getOpInfo)
+ return false;
+
+ struct LLVMOpInfo1 SymbolicOp;
+ SymbolicOp.Value = Value;
+ void *DisInfo = Dis->getDisInfoBlock();
+ if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
+ if (isBranch) {
+ LLVMSymbolLookupCallback SymbolLookUp =
+ Dis->getLLVMSymbolLookupCallback();
+ if (SymbolLookUp) {
+ uint64_t ReferenceType;
+ ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
+ const char *ReferenceName;
+ const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
+ &ReferenceName);
+ if (Name) {
+ SymbolicOp.AddSymbol.Name = Name;
+ SymbolicOp.AddSymbol.Present = true;
+ SymbolicOp.Value = 0;
+ }
+ else {
+ SymbolicOp.Value = Value;
+ }
+ if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
+ (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
+ }
+ else {
+ return false;
+ }
+ }
+ else {
+ return false;
+ }
+ }
+
+ MCContext *Ctx = Dis->getMCContext();
+ const MCExpr *Add = NULL;
+ if (SymbolicOp.AddSymbol.Present) {
+ if (SymbolicOp.AddSymbol.Name) {
+ StringRef Name(SymbolicOp.AddSymbol.Name);
+ MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
+ Add = MCSymbolRefExpr::Create(Sym, *Ctx);
+ } else {
+ Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
+ }
+ }
+
+ const MCExpr *Sub = NULL;
+ if (SymbolicOp.SubtractSymbol.Present) {
+ if (SymbolicOp.SubtractSymbol.Name) {
+ StringRef Name(SymbolicOp.SubtractSymbol.Name);
+ MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
+ Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
+ } else {
+ Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
+ }
+ }
+
+ const MCExpr *Off = NULL;
+ if (SymbolicOp.Value != 0)
+ Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
+
+ const MCExpr *Expr;
+ if (Sub) {
+ const MCExpr *LHS;
+ if (Add)
+ LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
+ else
+ LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
+ if (Off != 0)
+ Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
+ else
+ Expr = LHS;
+ } else if (Add) {
+ if (Off != 0)
+ Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
+ else
+ Expr = Add;
+ } else {
+ if (Off != 0)
+ Expr = Off;
+ else
+ Expr = MCConstantExpr::Create(0, *Ctx);
+ }
+
+ if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
+ MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
+ else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
+ MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
+ else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
+ MI.addOperand(MCOperand::CreateExpr(Expr));
+ else
+ assert(0 && "bad SymbolicOp.VariantKind");
+
+ return true;
+}
+
+/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
+/// referenced by a load instruction with the base register that is the Pc.
+/// These can often be values in a literal pool near the Address of the
+/// instruction. The Address of the instruction and its immediate Value are
+/// used as a possible literal pool entry. The SymbolLookUp call back will
+/// return the name of a symbol referenced by the the literal pool's entry if
+/// the referenced address is that of a symbol. Or it will return a pointer to
+/// a literal 'C' string if the referenced address of the literal pool's entry
+/// is an address into a section with 'C' string literals.
+static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
+ const void *Decoder) {
+ const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
+ LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
+ if (SymbolLookUp) {
+ void *DisInfo = Dis->getDisInfoBlock();
+ uint64_t ReferenceType;
+ ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
+ const char *ReferenceName;
+ (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
+ if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
+ ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
+ (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
+ }
}
// Thumb1 instructions don't have explicit S bits. Rather, they
// encoding, but rather get their predicates from IT context. We need
// to fix up the predicate operands using this context information as a
// post-pass.
-void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
+MCDisassembler::DecodeStatus
+ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
+ MCDisassembler::DecodeStatus S = Success;
+
// A few instructions actually have predicates encoded in them. Don't
// try to overwrite it if we're seeing one of those.
switch (MI.getOpcode()) {
case ARM::tBcc:
case ARM::t2Bcc:
- return;
+ case ARM::tCBZ:
+ case ARM::tCBNZ:
+ case ARM::tCPS:
+ case ARM::t2CPS3p:
+ case ARM::t2CPS2p:
+ case ARM::t2CPS1p:
+ case ARM::tMOVSr:
+ case ARM::tSETEND:
+ // Some instructions (mostly conditional branches) are not
+ // allowed in IT blocks.
+ if (!ITBlock.empty())
+ S = SoftFail;
+ else
+ return Success;
+ break;
+ case ARM::tB:
+ case ARM::t2B:
+ case ARM::t2TBB:
+ case ARM::t2TBH:
+ // Some instructions (mostly unconditional branches) can
+ // only appears at the end of, or outside of, an IT.
+ if (ITBlock.size() > 1)
+ S = SoftFail;
+ break;
default:
break;
}
MI.insert(I, MCOperand::CreateReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
- return;
+ return S;
}
}
MI.insert(I, MCOperand::CreateReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+
+ return S;
}
// Thumb VFP instructions are a special case. Because we share their
DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
- raw_ostream &os) const {
+ raw_ostream &os,
+ raw_ostream &cs) const {
+ CommentStream = &cs;
+
uint8_t bytes[4];
+ assert((STI.getFeatureBits() & ARM::ModeThumb) &&
+ "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
+
// We want to read exactly 2 bytes of data.
if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
Size = 0;
- return Fail;
+ return MCDisassembler::Fail;
}
uint16_t insn16 = (bytes[1] << 8) | bytes[0];
- DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
- if (result != Fail) {
+ DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 2;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
MI.clear();
- result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
+ result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
if (result) {
Size = 2;
bool InITBlock = !ITBlock.empty();
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
AddThumb1SBit(MI, InITBlock);
return result;
}
MI.clear();
- result = decodeThumb2Instruction16(MI, insn16, Address, this);
- if (result != Fail) {
+ result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 2;
- AddThumbPredicate(MI);
+
+ // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
+ // the Thumb predicate.
+ if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
+ result = MCDisassembler::SoftFail;
+
+ Check(result, AddThumbPredicate(MI));
// If we find an IT instruction, we need to parse its condition
// code and mask operands so that we can apply them correctly
// to the subsequent instructions.
if (MI.getOpcode() == ARM::t2IT) {
+
// (3 - the number of trailing zeros) is the number of then / else.
unsigned firstcond = MI.getOperand(0).getImm();
unsigned Mask = MI.getOperand(1).getImm();
// We want to read exactly 4 bytes of data.
if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
Size = 0;
- return Fail;
+ return MCDisassembler::Fail;
}
uint32_t insn32 = (bytes[3] << 8) |
(bytes[1] << 24) |
(bytes[0] << 16);
MI.clear();
- result = decodeThumbInstruction32(MI, insn32, Address, this);
- if (result != Fail) {
+ result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
bool InITBlock = ITBlock.size();
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
AddThumb1SBit(MI, InITBlock);
return result;
}
MI.clear();
- result = decodeThumb2Instruction32(MI, insn32, Address, this);
- if (result != Fail) {
+ result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
MI.clear();
- result = decodeCommonInstruction32(MI, insn32, Address, this);
- if (result != Fail) {
- Size = 4;
- AddThumbPredicate(MI);
- return result;
- }
-
- MI.clear();
- result = decodeVFPInstruction32(MI, insn32, Address, this);
- if (result != Fail) {
+ result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
UpdateThumbVFPPredicate(MI);
return result;
}
MI.clear();
- result = decodeNEONDupInstruction32(MI, insn32, Address, this);
- if (result != Fail) {
+ result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
uint32_t NEONLdStInsn = insn32;
NEONLdStInsn &= 0xF0FFFFFF;
NEONLdStInsn |= 0x04000000;
- result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
- if (result != Fail) {
+ result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
}
NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
NEONDataInsn |= 0x12000000; // Set bits 28 and 25
- result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
- if (result != Fail) {
+ result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
+ if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
}
Size = 0;
- return Fail;
+ return MCDisassembler::Fail;
}
static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 15)
- return Fail;
+ return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus
DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
- if (RegNo == 15) return Fail;
+ if (RegNo == 15) return MCDisassembler::Fail;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 7)
- return Fail;
+ return MCDisassembler::Fail;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}
Register = ARM::R12;
break;
default:
- return Fail;
+ return MCDisassembler::Fail;
}
Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
- if (RegNo == 13 || RegNo == 15) return Fail;
+ if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 31)
- return Fail;
+ return MCDisassembler::Fail;
unsigned Register = SPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
+ return MCDisassembler::Success;
}
static const unsigned DPRDecoderTable[] = {
static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 31)
- return Fail;
+ return MCDisassembler::Fail;
unsigned Register = DPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 7)
- return Fail;
+ return MCDisassembler::Fail;
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
}
DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 15)
- return Fail;
+ return MCDisassembler::Fail;
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 31)
- return Fail;
+ return MCDisassembler::Fail;
RegNo >>= 1;
unsigned Register = QPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- if (Val == 0xF) return Fail;
+ if (Val == 0xF) return MCDisassembler::Fail;
// AL predicate is not allowed on Thumb1 branches.
if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
- return Fail;
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
if (Val == ARMCC::AL) {
Inst.addOperand(MCOperand::CreateReg(0));
} else
Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
else
Inst.addOperand(MCOperand::CreateReg(0));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
uint32_t imm = Val & 0xFF;
uint32_t rot = (Val & 0xF00) >> 7;
- uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
+ uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Inst.addOperand(MCOperand::CreateImm(rot_imm));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction32(Val, 0, 4);
unsigned type = fieldFromInstruction32(Val, 5, 2);
unsigned imm = fieldFromInstruction32(Val, 7, 5);
// Register-immediate
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) {
static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction32(Val, 0, 4);
unsigned type = fieldFromInstruction32(Val, 5, 2);
unsigned Rs = fieldFromInstruction32(Val, 8, 4);
// Register-register
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
+ return MCDisassembler::Fail;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) {
static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
+
+ bool writebackLoad = false;
+ unsigned writebackReg = 0;
+ switch (Inst.getOpcode()) {
+ default:
+ break;
+ case ARM::LDMIA_UPD:
+ case ARM::LDMDB_UPD:
+ case ARM::LDMIB_UPD:
+ case ARM::LDMDA_UPD:
+ case ARM::t2LDMIA_UPD:
+ case ARM::t2LDMDB_UPD:
+ writebackLoad = true;
+ writebackReg = Inst.getOperand(0).getReg();
+ break;
+ }
// Empty register lists are not allowed.
- if (CountPopulation_32(Val) == 0) return Fail;
+ if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
- CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // Writeback not allowed if Rn is in the target list.
+ if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
+ Check(S, MCDisassembler::SoftFail);
}
}
static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Vd = fieldFromInstruction32(Val, 8, 4);
unsigned regs = Val & 0xFF;
- CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
+ return MCDisassembler::Fail;
for (unsigned i = 0; i < (regs - 1); ++i) {
- CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
+ if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
+ return MCDisassembler::Fail;
}
return S;
static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Vd = fieldFromInstruction32(Val, 8, 4);
unsigned regs = (Val & 0xFF) / 2;
- CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
+ return MCDisassembler::Fail;
for (unsigned i = 0; i < (regs - 1); ++i) {
- CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
+ return MCDisassembler::Fail;
}
return S;
// create the final mask.
unsigned msb = fieldFromInstruction32(Val, 5, 5);
unsigned lsb = fieldFromInstruction32(Val, 0, 5);
- uint32_t msb_mask = (1 << (msb+1)) - 1;
- uint32_t lsb_mask = (1 << lsb) - 1;
+
+ DecodeStatus S = MCDisassembler::Success;
+ if (lsb > msb) Check(S, MCDisassembler::SoftFail);
+
+ uint32_t msb_mask = 0xFFFFFFFF;
+ if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
+ uint32_t lsb_mask = (1U << lsb) - 1;
+
Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
- return Success;
+ return S;
}
static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
case ARM::STCL_PRE:
case ARM::STCL_POST:
case ARM::STCL_OPTION:
+ case ARM::t2LDC_OFFSET:
+ case ARM::t2LDC_PRE:
+ case ARM::t2LDC_POST:
+ case ARM::t2LDC_OPTION:
+ case ARM::t2LDCL_OFFSET:
+ case ARM::t2LDCL_PRE:
+ case ARM::t2LDCL_POST:
+ case ARM::t2LDCL_OPTION:
+ case ARM::t2STC_OFFSET:
+ case ARM::t2STC_PRE:
+ case ARM::t2STC_POST:
+ case ARM::t2STC_OPTION:
+ case ARM::t2STCL_OFFSET:
+ case ARM::t2STCL_PRE:
+ case ARM::t2STCL_POST:
+ case ARM::t2STCL_OPTION:
if (coproc == 0xA || coproc == 0xB)
- return Fail;
+ return MCDisassembler::Fail;
break;
default:
break;
Inst.addOperand(MCOperand::CreateImm(coproc));
Inst.addOperand(MCOperand::CreateImm(CRd));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+
switch (Inst.getOpcode()) {
- case ARM::LDC_OPTION:
- case ARM::LDCL_OPTION:
- case ARM::LDC2_OPTION:
- case ARM::LDC2L_OPTION:
- case ARM::STC_OPTION:
- case ARM::STCL_OPTION:
- case ARM::STC2_OPTION:
- case ARM::STC2L_OPTION:
- case ARM::LDCL_POST:
- case ARM::STCL_POST:
+ case ARM::t2LDC2_OFFSET:
+ case ARM::t2LDC2L_OFFSET:
+ case ARM::t2LDC2_PRE:
+ case ARM::t2LDC2L_PRE:
+ case ARM::t2STC2_OFFSET:
+ case ARM::t2STC2L_OFFSET:
+ case ARM::t2STC2_PRE:
+ case ARM::t2STC2L_PRE:
+ case ARM::LDC2_OFFSET:
+ case ARM::LDC2L_OFFSET:
+ case ARM::LDC2_PRE:
+ case ARM::LDC2L_PRE:
+ case ARM::STC2_OFFSET:
+ case ARM::STC2L_OFFSET:
+ case ARM::STC2_PRE:
+ case ARM::STC2L_PRE:
+ case ARM::t2LDC_OFFSET:
+ case ARM::t2LDCL_OFFSET:
+ case ARM::t2LDC_PRE:
+ case ARM::t2LDCL_PRE:
+ case ARM::t2STC_OFFSET:
+ case ARM::t2STCL_OFFSET:
+ case ARM::t2STC_PRE:
+ case ARM::t2STCL_PRE:
+ case ARM::LDC_OFFSET:
+ case ARM::LDCL_OFFSET:
+ case ARM::LDC_PRE:
+ case ARM::LDCL_PRE:
+ case ARM::STC_OFFSET:
+ case ARM::STCL_OFFSET:
+ case ARM::STC_PRE:
+ case ARM::STCL_PRE:
+ imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
+ Inst.addOperand(MCOperand::CreateImm(imm));
+ break;
+ case ARM::t2LDC2_POST:
+ case ARM::t2LDC2L_POST:
+ case ARM::t2STC2_POST:
+ case ARM::t2STC2L_POST:
+ case ARM::LDC2_POST:
case ARM::LDC2L_POST:
+ case ARM::STC2_POST:
case ARM::STC2L_POST:
- break;
- default:
- Inst.addOperand(MCOperand::CreateReg(0));
- break;
- }
-
- unsigned P = fieldFromInstruction32(Insn, 24, 1);
- unsigned W = fieldFromInstruction32(Insn, 21, 1);
-
- bool writeback = (P == 0) || (W == 1);
- unsigned idx_mode = 0;
- if (P && writeback)
- idx_mode = ARMII::IndexModePre;
- else if (!P && writeback)
- idx_mode = ARMII::IndexModePost;
-
- switch (Inst.getOpcode()) {
+ case ARM::t2LDC_POST:
+ case ARM::t2LDCL_POST:
+ case ARM::t2STC_POST:
+ case ARM::t2STCL_POST:
+ case ARM::LDC_POST:
case ARM::LDCL_POST:
+ case ARM::STC_POST:
case ARM::STCL_POST:
- case ARM::LDC2L_POST:
- case ARM::STC2L_POST:
imm |= U << 8;
- case ARM::LDC_OPTION:
- case ARM::LDCL_OPTION:
- case ARM::LDC2_OPTION:
- case ARM::LDC2L_OPTION:
- case ARM::STC_OPTION:
- case ARM::STCL_OPTION:
- case ARM::STC2_OPTION:
- case ARM::STC2L_OPTION:
- Inst.addOperand(MCOperand::CreateImm(imm));
- break;
+ // fall through.
default:
- if (U)
- Inst.addOperand(MCOperand::CreateImm(
- ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
- else
- Inst.addOperand(MCOperand::CreateImm(
- ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
+ // The 'option' variant doesn't encode 'U' in the immediate since
+ // the immediate is unsigned [0,255].
+ Inst.addOperand(MCOperand::CreateImm(imm));
break;
}
case ARM::STCL_PRE:
case ARM::STCL_POST:
case ARM::STCL_OPTION:
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
static DecodeStatus
DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
case ARM::STRT_POST_IMM:
case ARM::STRBT_POST_REG:
case ARM::STRBT_POST_IMM:
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
// On loads, the writeback operand comes after Rt.
switch (Inst.getOpcode()) {
case ARM::LDRBT_POST_IMM:
case ARM::LDRT_POST_REG:
case ARM::LDRT_POST_IMM:
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
ARM_AM::AddrOpc Op = ARM_AM::add;
if (!fieldFromInstruction32(Insn, 23, 1))
else if (!P && writeback)
idx_mode = ARMII::IndexModePost;
- if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
+ if (writeback && (Rn == 15 || Rn == Rt))
+ S = MCDisassembler::SoftFail; // UNPREDICTABLE
if (reg) {
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
switch( fieldFromInstruction32(Insn, 5, 2)) {
case 0:
Opc = ARM_AM::ror;
break;
default:
- return Fail;
+ return MCDisassembler::Fail;
}
unsigned amt = fieldFromInstruction32(Insn, 7, 5);
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
Inst.addOperand(MCOperand::CreateImm(tmp));
}
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 13, 4);
unsigned Rm = fieldFromInstruction32(Val, 0, 4);
break;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
unsigned shift;
if (U)
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
static DecodeStatus
DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
- if (Rt & 0x1) return Fail;
+ if (Rt & 0x1) return MCDisassembler::Fail;
+ break;
+ default:
break;
- default:
- break;
}
if (writeback) { // Writeback
case ARM::STRH:
case ARM::STRH_PRE:
case ARM::STRH_POST:
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
}
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
switch (Inst.getOpcode()) {
case ARM::STRD:
case ARM::STRD_PRE:
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
case ARM::LDRSB_POST:
case ARM::LDRHTr:
case ARM::LDRSBTr:
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
}
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
if (type) {
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
} else {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(U));
}
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned mode = fieldFromInstruction32(Insn, 23, 2);
}
Inst.addOperand(MCOperand::CreateImm(mode));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Inst.setOpcode(ARM::SRSIB_UPD);
break;
default:
- CHECK(S, Fail);
+ if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
}
// For stores (which become SRS's, the only operand is the mode.
return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
- CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail; // Tied
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
unsigned mode = fieldFromInstruction32(Insn, 0, 5);
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
// imod == '01' --> UNPREDICTABLE
// NOTE: Even though this is technically UNPREDICTABLE, we choose to
// return failure here. The '01' imod value is unprintable, so there's
// nothing useful we could do even if we returned UNPREDICTABLE.
- if (imod == 1) CHECK(S, Fail);
+ if (imod == 1) return MCDisassembler::Fail;
if (imod && M) {
Inst.setOpcode(ARM::CPS3p);
Inst.setOpcode(ARM::CPS2p);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(iflags));
- if (mode) CHECK(S, Unpredictable);
+ if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
- if (iflags) CHECK(S, Unpredictable);
+ if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
- CHECK(S, Unpredictable);
+ S = MCDisassembler::SoftFail;
}
return S;
unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
unsigned mode = fieldFromInstruction32(Insn, 0, 5);
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
// imod == '01' --> UNPREDICTABLE
// NOTE: Even though this is technically UNPREDICTABLE, we choose to
// return failure here. The '01' imod value is unprintable, so there's
// nothing useful we could do even if we returned UNPREDICTABLE.
- if (imod == 1) CHECK(S, Fail);
+ if (imod == 1) return MCDisassembler::Fail;
if (imod && M) {
Inst.setOpcode(ARM::t2CPS3p);
Inst.setOpcode(ARM::t2CPS2p);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(iflags));
- if (mode) CHECK(S, Unpredictable);
+ if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::t2CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
- if (iflags) CHECK(S, Unpredictable);
+ if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::t2CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
- CHECK(S, Unpredictable);
+ S = MCDisassembler::SoftFail;
}
return S;
}
+static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
+ unsigned imm = 0;
+
+ imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
+ imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
+ imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
+ imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
+
+ if (Inst.getOpcode() == ARM::t2MOVTi16)
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
+ Inst.addOperand(MCOperand::CreateImm(imm));
+
+ return S;
+}
+
+static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+ unsigned imm = 0;
+
+ imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
+ imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
+
+ if (Inst.getOpcode() == ARM::MOVTi16)
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
+ Inst.addOperand(MCOperand::CreateImm(imm));
+
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
- CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
+ return MCDisassembler::Fail;
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned add = fieldFromInstruction32(Val, 12, 1);
unsigned imm = fieldFromInstruction32(Val, 0, 12);
unsigned Rn = fieldFromInstruction32(Val, 13, 4);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN;
Inst.addOperand(MCOperand::CreateImm(imm));
+ if (Rn == 15)
+ tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
return S;
}
static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 9, 4);
unsigned U = fieldFromInstruction32(Val, 8, 1);
unsigned imm = fieldFromInstruction32(Val, 0, 8);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
if (U)
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
static DecodeStatus
DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
return S;
}
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
+ 4, Inst, Decoder))
+ Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
-static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
- uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(64 - Val));
- return Success;
-}
-
static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction32(Val, 0, 4);
unsigned align = fieldFromInstruction32(Val, 4, 2);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
if (!align)
Inst.addOperand(MCOperand::CreateImm(0));
else
static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
// First output register
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
// Second output register
switch (Inst.getOpcode()) {
- case ARM::VLD1q8:
- case ARM::VLD1q16:
- case ARM::VLD1q32:
- case ARM::VLD1q64:
- case ARM::VLD1q8_UPD:
- case ARM::VLD1q16_UPD:
- case ARM::VLD1q32_UPD:
- case ARM::VLD1q64_UPD:
- case ARM::VLD1d8T:
- case ARM::VLD1d16T:
- case ARM::VLD1d32T:
- case ARM::VLD1d64T:
- case ARM::VLD1d8T_UPD:
- case ARM::VLD1d16T_UPD:
- case ARM::VLD1d32T_UPD:
- case ARM::VLD1d64T_UPD:
- case ARM::VLD1d8Q:
- case ARM::VLD1d16Q:
- case ARM::VLD1d32Q:
- case ARM::VLD1d64Q:
- case ARM::VLD1d8Q_UPD:
- case ARM::VLD1d16Q_UPD:
- case ARM::VLD1d32Q_UPD:
- case ARM::VLD1d64Q_UPD:
- case ARM::VLD2d8:
- case ARM::VLD2d16:
- case ARM::VLD2d32:
- case ARM::VLD2d8_UPD:
- case ARM::VLD2d16_UPD:
- case ARM::VLD2d32_UPD:
- case ARM::VLD2q8:
- case ARM::VLD2q16:
- case ARM::VLD2q32:
- case ARM::VLD2q8_UPD:
- case ARM::VLD2q16_UPD:
- case ARM::VLD2q32_UPD:
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
- break;
- case ARM::VLD2b8:
- case ARM::VLD2b16:
- case ARM::VLD2b32:
- case ARM::VLD2b8_UPD:
- case ARM::VLD2b16_UPD:
- case ARM::VLD2b32_UPD:
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
case ARM::VLD3q8:
case ARM::VLD3q16:
case ARM::VLD3q32:
case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
default:
break;
}
// Third output register
switch(Inst.getOpcode()) {
- case ARM::VLD1d8T:
- case ARM::VLD1d16T:
- case ARM::VLD1d32T:
- case ARM::VLD1d64T:
- case ARM::VLD1d8T_UPD:
- case ARM::VLD1d16T_UPD:
- case ARM::VLD1d32T_UPD:
- case ARM::VLD1d64T_UPD:
- case ARM::VLD1d8Q:
- case ARM::VLD1d16Q:
- case ARM::VLD1d32Q:
- case ARM::VLD1d64Q:
- case ARM::VLD1d8Q_UPD:
- case ARM::VLD1d16Q_UPD:
- case ARM::VLD1d32Q_UPD:
- case ARM::VLD1d64Q_UPD:
- case ARM::VLD2q8:
- case ARM::VLD2q16:
- case ARM::VLD2q32:
- case ARM::VLD2q8_UPD:
- case ARM::VLD2q16_UPD:
- case ARM::VLD2q32_UPD:
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
case ARM::VLD3q8:
case ARM::VLD3q16:
case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
// Fourth output register
switch (Inst.getOpcode()) {
- case ARM::VLD1d8Q:
- case ARM::VLD1d16Q:
- case ARM::VLD1d32Q:
- case ARM::VLD1d64Q:
- case ARM::VLD1d8Q_UPD:
- case ARM::VLD1d16Q_UPD:
- case ARM::VLD1d32Q_UPD:
- case ARM::VLD1d64Q_UPD:
- case ARM::VLD2q8:
- case ARM::VLD2q16:
- case ARM::VLD2q32:
- case ARM::VLD2q8_UPD:
- case ARM::VLD2q16_UPD:
- case ARM::VLD2q32_UPD:
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
case ARM::VLD4q8:
case ARM::VLD4q16:
case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
// Writeback operand
switch (Inst.getOpcode()) {
- case ARM::VLD1d8_UPD:
- case ARM::VLD1d16_UPD:
- case ARM::VLD1d32_UPD:
- case ARM::VLD1d64_UPD:
- case ARM::VLD1q8_UPD:
- case ARM::VLD1q16_UPD:
- case ARM::VLD1q32_UPD:
- case ARM::VLD1q64_UPD:
- case ARM::VLD1d8T_UPD:
- case ARM::VLD1d16T_UPD:
- case ARM::VLD1d32T_UPD:
- case ARM::VLD1d64T_UPD:
- case ARM::VLD1d8Q_UPD:
- case ARM::VLD1d16Q_UPD:
- case ARM::VLD1d32Q_UPD:
- case ARM::VLD1d64Q_UPD:
- case ARM::VLD2d8_UPD:
- case ARM::VLD2d16_UPD:
- case ARM::VLD2d32_UPD:
- case ARM::VLD2q8_UPD:
- case ARM::VLD2q16_UPD:
- case ARM::VLD2q32_UPD:
- case ARM::VLD2b8_UPD:
- case ARM::VLD2b16_UPD:
- case ARM::VLD2b32_UPD:
+ case ARM::VLD1d8wb_fixed:
+ case ARM::VLD1d16wb_fixed:
+ case ARM::VLD1d32wb_fixed:
+ case ARM::VLD1d64wb_fixed:
+ case ARM::VLD1d8wb_register:
+ case ARM::VLD1d16wb_register:
+ case ARM::VLD1d32wb_register:
+ case ARM::VLD1d64wb_register:
+ case ARM::VLD1q8wb_fixed:
+ case ARM::VLD1q16wb_fixed:
+ case ARM::VLD1q32wb_fixed:
+ case ARM::VLD1q64wb_fixed:
+ case ARM::VLD1q8wb_register:
+ case ARM::VLD1q16wb_register:
+ case ARM::VLD1q32wb_register:
+ case ARM::VLD1q64wb_register:
+ case ARM::VLD1d8Twb_fixed:
+ case ARM::VLD1d8Twb_register:
+ case ARM::VLD1d16Twb_fixed:
+ case ARM::VLD1d16Twb_register:
+ case ARM::VLD1d32Twb_fixed:
+ case ARM::VLD1d32Twb_register:
+ case ARM::VLD1d64Twb_fixed:
+ case ARM::VLD1d64Twb_register:
+ case ARM::VLD1d8Qwb_fixed:
+ case ARM::VLD1d8Qwb_register:
+ case ARM::VLD1d16Qwb_fixed:
+ case ARM::VLD1d16Qwb_register:
+ case ARM::VLD1d32Qwb_fixed:
+ case ARM::VLD1d32Qwb_register:
+ case ARM::VLD1d64Qwb_fixed:
+ case ARM::VLD1d64Qwb_register:
+ case ARM::VLD2d8wb_fixed:
+ case ARM::VLD2d16wb_fixed:
+ case ARM::VLD2d32wb_fixed:
+ case ARM::VLD2q8wb_fixed:
+ case ARM::VLD2q16wb_fixed:
+ case ARM::VLD2q32wb_fixed:
+ case ARM::VLD2d8wb_register:
+ case ARM::VLD2d16wb_register:
+ case ARM::VLD2d32wb_register:
+ case ARM::VLD2q8wb_register:
+ case ARM::VLD2q16wb_register:
+ case ARM::VLD2q32wb_register:
+ case ARM::VLD2b8wb_fixed:
+ case ARM::VLD2b16wb_fixed:
+ case ARM::VLD2b32wb_fixed:
+ case ARM::VLD2b8wb_register:
+ case ARM::VLD2b16wb_register:
+ case ARM::VLD2b32wb_register:
case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD:
case ARM::VLD3d32_UPD:
case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD:
- CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
}
// AddrMode6 Base (register+alignment)
- CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
// AddrMode6 Offset (register)
- if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
- else if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ switch (Inst.getOpcode()) {
+ default:
+ // The below have been updated to have explicit am6offset split
+ // between fixed and register offset. For those instructions not
+ // yet updated, we need to add an additional reg0 operand for the
+ // fixed variant.
+ //
+ // The fixed offset encodes as Rm == 0xd, so we check for that.
+ if (Rm == 0xd) {
+ Inst.addOperand(MCOperand::CreateReg(0));
+ break;
+ }
+ // Fall through to handle the register offset variant.
+ case ARM::VLD1d8wb_fixed:
+ case ARM::VLD1d16wb_fixed:
+ case ARM::VLD1d32wb_fixed:
+ case ARM::VLD1d64wb_fixed:
+ case ARM::VLD1d8Twb_fixed:
+ case ARM::VLD1d16Twb_fixed:
+ case ARM::VLD1d32Twb_fixed:
+ case ARM::VLD1d64Twb_fixed:
+ case ARM::VLD1d8Qwb_fixed:
+ case ARM::VLD1d16Qwb_fixed:
+ case ARM::VLD1d32Qwb_fixed:
+ case ARM::VLD1d64Qwb_fixed:
+ case ARM::VLD1d8wb_register:
+ case ARM::VLD1d16wb_register:
+ case ARM::VLD1d32wb_register:
+ case ARM::VLD1d64wb_register:
+ case ARM::VLD1q8wb_fixed:
+ case ARM::VLD1q16wb_fixed:
+ case ARM::VLD1q32wb_fixed:
+ case ARM::VLD1q64wb_fixed:
+ case ARM::VLD1q8wb_register:
+ case ARM::VLD1q16wb_register:
+ case ARM::VLD1q32wb_register:
+ case ARM::VLD1q64wb_register:
+ // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
+ // variant encodes Rm == 0xf. Anything else is a register offset post-
+ // increment and we need to add the register operand to the instruction.
+ if (Rm != 0xD && Rm != 0xF &&
+ !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
}
return S;
static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
// Writeback Operand
switch (Inst.getOpcode()) {
- case ARM::VST1d8_UPD:
- case ARM::VST1d16_UPD:
- case ARM::VST1d32_UPD:
- case ARM::VST1d64_UPD:
- case ARM::VST1q8_UPD:
- case ARM::VST1q16_UPD:
- case ARM::VST1q32_UPD:
- case ARM::VST1q64_UPD:
- case ARM::VST1d8T_UPD:
- case ARM::VST1d16T_UPD:
- case ARM::VST1d32T_UPD:
- case ARM::VST1d64T_UPD:
- case ARM::VST1d8Q_UPD:
- case ARM::VST1d16Q_UPD:
- case ARM::VST1d32Q_UPD:
- case ARM::VST1d64Q_UPD:
- case ARM::VST2d8_UPD:
- case ARM::VST2d16_UPD:
- case ARM::VST2d32_UPD:
- case ARM::VST2q8_UPD:
- case ARM::VST2q16_UPD:
- case ARM::VST2q32_UPD:
- case ARM::VST2b8_UPD:
- case ARM::VST2b16_UPD:
- case ARM::VST2b32_UPD:
+ case ARM::VST1d8wb_fixed:
+ case ARM::VST1d16wb_fixed:
+ case ARM::VST1d32wb_fixed:
+ case ARM::VST1d64wb_fixed:
+ case ARM::VST1d8wb_register:
+ case ARM::VST1d16wb_register:
+ case ARM::VST1d32wb_register:
+ case ARM::VST1d64wb_register:
+ case ARM::VST1q8wb_fixed:
+ case ARM::VST1q16wb_fixed:
+ case ARM::VST1q32wb_fixed:
+ case ARM::VST1q64wb_fixed:
+ case ARM::VST1q8wb_register:
+ case ARM::VST1q16wb_register:
+ case ARM::VST1q32wb_register:
+ case ARM::VST1q64wb_register:
+ case ARM::VST1d8Twb_fixed:
+ case ARM::VST1d16Twb_fixed:
+ case ARM::VST1d32Twb_fixed:
+ case ARM::VST1d64Twb_fixed:
+ case ARM::VST1d8Twb_register:
+ case ARM::VST1d16Twb_register:
+ case ARM::VST1d32Twb_register:
+ case ARM::VST1d64Twb_register:
+ case ARM::VST1d8Qwb_fixed:
+ case ARM::VST1d16Qwb_fixed:
+ case ARM::VST1d32Qwb_fixed:
+ case ARM::VST1d64Qwb_fixed:
+ case ARM::VST1d8Qwb_register:
+ case ARM::VST1d16Qwb_register:
+ case ARM::VST1d32Qwb_register:
+ case ARM::VST1d64Qwb_register:
+ case ARM::VST2d8wb_fixed:
+ case ARM::VST2d16wb_fixed:
+ case ARM::VST2d32wb_fixed:
+ case ARM::VST2d8wb_register:
+ case ARM::VST2d16wb_register:
+ case ARM::VST2d32wb_register:
+ case ARM::VST2q8wb_fixed:
+ case ARM::VST2q16wb_fixed:
+ case ARM::VST2q32wb_fixed:
+ case ARM::VST2q8wb_register:
+ case ARM::VST2q16wb_register:
+ case ARM::VST2q32wb_register:
+ case ARM::VST2b8wb_fixed:
+ case ARM::VST2b16wb_fixed:
+ case ARM::VST2b32wb_fixed:
+ case ARM::VST2b8wb_register:
+ case ARM::VST2b16wb_register:
+ case ARM::VST2b32wb_register:
case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD:
case ARM::VST3d32_UPD:
case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD:
- CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
}
// AddrMode6 Base (register+alignment)
- CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
// AddrMode6 Offset (register)
- if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
- else if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ switch (Inst.getOpcode()) {
+ default:
+ if (Rm == 0xD)
+ Inst.addOperand(MCOperand::CreateReg(0));
+ else if (Rm != 0xF) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+ break;
+ case ARM::VST1d8wb_fixed:
+ case ARM::VST1d16wb_fixed:
+ case ARM::VST1d32wb_fixed:
+ case ARM::VST1d64wb_fixed:
+ case ARM::VST1q8wb_fixed:
+ case ARM::VST1q16wb_fixed:
+ case ARM::VST1q32wb_fixed:
+ case ARM::VST1q64wb_fixed:
+ break;
}
+
// First input register
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
// Second input register
switch (Inst.getOpcode()) {
- case ARM::VST1q8:
- case ARM::VST1q16:
- case ARM::VST1q32:
- case ARM::VST1q64:
- case ARM::VST1q8_UPD:
- case ARM::VST1q16_UPD:
- case ARM::VST1q32_UPD:
- case ARM::VST1q64_UPD:
- case ARM::VST1d8T:
- case ARM::VST1d16T:
- case ARM::VST1d32T:
- case ARM::VST1d64T:
- case ARM::VST1d8T_UPD:
- case ARM::VST1d16T_UPD:
- case ARM::VST1d32T_UPD:
- case ARM::VST1d64T_UPD:
- case ARM::VST1d8Q:
- case ARM::VST1d16Q:
- case ARM::VST1d32Q:
- case ARM::VST1d64Q:
- case ARM::VST1d8Q_UPD:
- case ARM::VST1d16Q_UPD:
- case ARM::VST1d32Q_UPD:
- case ARM::VST1d64Q_UPD:
- case ARM::VST2d8:
- case ARM::VST2d16:
- case ARM::VST2d32:
- case ARM::VST2d8_UPD:
- case ARM::VST2d16_UPD:
- case ARM::VST2d32_UPD:
- case ARM::VST2q8:
- case ARM::VST2q16:
- case ARM::VST2q32:
- case ARM::VST2q8_UPD:
- case ARM::VST2q16_UPD:
- case ARM::VST2q32_UPD:
case ARM::VST3d8:
case ARM::VST3d16:
case ARM::VST3d32:
case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
- break;
- case ARM::VST2b8:
- case ARM::VST2b16:
- case ARM::VST2b32:
- case ARM::VST2b8_UPD:
- case ARM::VST2b16_UPD:
- case ARM::VST2b32_UPD:
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ break;
case ARM::VST3q8:
case ARM::VST3q16:
case ARM::VST3q32:
case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
// Third input register
switch (Inst.getOpcode()) {
- case ARM::VST1d8T:
- case ARM::VST1d16T:
- case ARM::VST1d32T:
- case ARM::VST1d64T:
- case ARM::VST1d8T_UPD:
- case ARM::VST1d16T_UPD:
- case ARM::VST1d32T_UPD:
- case ARM::VST1d64T_UPD:
- case ARM::VST1d8Q:
- case ARM::VST1d16Q:
- case ARM::VST1d32Q:
- case ARM::VST1d64Q:
- case ARM::VST1d8Q_UPD:
- case ARM::VST1d16Q_UPD:
- case ARM::VST1d32Q_UPD:
- case ARM::VST1d64Q_UPD:
- case ARM::VST2q8:
- case ARM::VST2q16:
- case ARM::VST2q32:
- case ARM::VST2q8_UPD:
- case ARM::VST2q16_UPD:
- case ARM::VST2q32_UPD:
case ARM::VST3d8:
case ARM::VST3d16:
case ARM::VST3d32:
case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
case ARM::VST3q8:
case ARM::VST3q16:
case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
// Fourth input register
switch (Inst.getOpcode()) {
- case ARM::VST1d8Q:
- case ARM::VST1d16Q:
- case ARM::VST1d32Q:
- case ARM::VST1d64Q:
- case ARM::VST1d8Q_UPD:
- case ARM::VST1d16Q_UPD:
- case ARM::VST1d32Q_UPD:
- case ARM::VST1d64Q_UPD:
- case ARM::VST2q8:
- case ARM::VST2q16:
- case ARM::VST2q32:
- case ARM::VST2q8_UPD:
- case ARM::VST2q16_UPD:
- case ARM::VST2q32_UPD:
case ARM::VST4d8:
case ARM::VST4d16:
case ARM::VST4d32:
case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
case ARM::VST4q8:
case ARM::VST4q16:
case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD:
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned align = fieldFromInstruction32(Insn, 4, 1);
unsigned size = fieldFromInstruction32(Insn, 6, 2);
- unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
align *= (1 << size);
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- if (regs == 2) {
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
- }
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
- if (Rm == 0xD)
- Inst.addOperand(MCOperand::CreateReg(0));
- else if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- }
+ // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
+ // variant encodes Rm == 0xf. Anything else is a register offset post-
+ // increment and we need to add the register operand to the instruction.
+ if (Rm != 0xD && Rm != 0xF &&
+ !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
align *= 2*size;
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
else if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
}
return S;
static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(0));
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
else if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
}
return S;
static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
}
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
else if (Rm != 0xF) {
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
}
return S;
static DecodeStatus
DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
unsigned Q = fieldFromInstruction32(Insn, 6, 1);
if (Q) {
- CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
} else {
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
}
Inst.addOperand(MCOperand::CreateImm(imm));
case ARM::VORRiv2i32:
case ARM::VBICiv4i16:
case ARM::VBICiv2i32:
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
case ARM::VORRiv8i16:
case ARM::VORRiv4i32:
case ARM::VBICiv8i16:
case ARM::VBICiv4i32:
- CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
break;
default:
break;
static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
unsigned size = fieldFromInstruction32(Insn, 18, 2);
- CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(8 << size));
return S;
static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(8 - Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(16 - Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(32 - Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(64 - Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
unsigned op = fieldFromInstruction32(Insn, 6, 1);
- unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
if (op) {
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail; // Writeback
}
- for (unsigned i = 0; i < length; ++i) {
- CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
- }
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
- CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
-static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
- uint64_t Address, const void *Decoder) {
- // The immediate needs to be a fully instantiated float. However, the
- // auto-generated decoder is only able to fill in some of the bits
- // necessary. For instance, the 'b' bit is replicated multiple times,
- // and is even present in inverted form in one bit. We do a little
- // binary parsing here to fill in those missing bits, and then
- // reinterpret it all as a float.
- union {
- uint32_t integer;
- float fp;
- } fp_conv;
-
- fp_conv.integer = Val;
- uint32_t b = fieldFromInstruction32(Val, 25, 1);
- fp_conv.integer |= b << 26;
- fp_conv.integer |= b << 27;
- fp_conv.integer |= b << 28;
- fp_conv.integer |= b << 29;
- fp_conv.integer |= (~b & 0x1) << 30;
-
- Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
- return Success;
-}
-
static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned dst = fieldFromInstruction16(Insn, 8, 3);
unsigned imm = fieldFromInstruction16(Insn, 0, 8);
- CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
+ if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
+ return MCDisassembler::Fail;
switch(Inst.getOpcode()) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case ARM::tADR:
break; // tADR does not explicitly represent the PC as an operand.
case ARM::tADDrSPi:
static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 0, 3);
unsigned Rm = fieldFromInstruction32(Val, 3, 3);
- CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 0, 3);
unsigned imm = fieldFromInstruction32(Val, 3, 5);
- CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
return S;
static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Val << 2));
+ unsigned imm = Val << 2;
+
+ Inst.addOperand(MCOperand::CreateImm(imm));
+ tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateImm(Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 6, 4);
unsigned Rm = fieldFromInstruction32(Val, 2, 4);
unsigned imm = fieldFromInstruction32(Val, 0, 2);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
return S;
static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
switch (Inst.getOpcode()) {
case ARM::t2PLDs:
break;
default: {
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
}
}
Inst.addOperand(MCOperand::CreateReg(ARM::PC));
break;
default:
- return Fail;
+ return MCDisassembler::Fail;
}
int imm = fieldFromInstruction32(Insn, 0, 12);
unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
- CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
+ if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
if (!(Val & 0x100)) imm *= -1;
Inst.addOperand(MCOperand::CreateImm(imm << 2));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 9, 4);
unsigned imm = fieldFromInstruction32(Val, 0, 9);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
+
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rn = fieldFromInstruction32(Val, 8, 4);
+ unsigned imm = fieldFromInstruction32(Val, 0, 8);
+
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::CreateImm(imm));
return S;
}
static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
int imm = Val & 0xFF;
- if (!(Val & 0x100)) imm *= -1;
+ if (Val == 0)
+ imm = INT32_MIN;
+ else if (!(Val & 0x100))
+ imm *= -1;
Inst.addOperand(MCOperand::CreateImm(imm));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 9, 4);
unsigned imm = fieldFromInstruction32(Val, 0, 9);
case ARM::t2LDRHT:
case ARM::t2LDRSBT:
case ARM::t2LDRSHT:
+ case ARM::t2STRT:
+ case ARM::t2STRBT:
+ case ARM::t2STRHT:
imm |= 0x100;
break;
default:
break;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
+static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned addr = fieldFromInstruction32(Insn, 0, 8);
+ addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
+ addr |= Rn << 9;
+ unsigned load = fieldFromInstruction32(Insn, 20, 1);
+
+ if (!load) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ if (load) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ }
+
+ if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Val, 13, 4);
unsigned imm = fieldFromInstruction32(Val, 0, 12);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
return S;
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateImm(imm));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
if (Inst.getOpcode() == ARM::tADDrSP) {
unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
}
return S;
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(flags));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned add = fieldFromInstruction32(Insn, 4, 1);
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(add));
return S;
static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
- return Success;
+ if (!tryAddingSymbolicOperand(Address,
+ (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
+ true, 4, Inst, Decoder))
+ Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0xA || Val == 0xB)
- return Fail;
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
- return Success;
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus
+DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
+
+ if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ return S;
}
static DecodeStatus
DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned pred = fieldFromInstruction32(Insn, 22, 4);
if (pred == 0xE || pred == 0xF) {
unsigned opc = fieldFromInstruction32(Insn, 4, 28);
switch (opc) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0xf3bf8f4:
Inst.setOpcode(ARM::t2DSB);
break;
break;
case 0xf3bf8f6:
Inst.setOpcode(ARM::t2ISB);
- return Success;
+ break;
}
unsigned imm = fieldFromInstruction32(Insn, 0, 4);
brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
- CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
Inst.addOperand(MCOperand::CreateImm(imm));
}
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus
DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder){
Inst.addOperand(MCOperand::CreateImm(Val << 1));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder){
Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
switch (Val) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0xF: // SY
case 0xE: // ST
case 0xB: // ISH
}
Inst.addOperand(MCOperand::CreateImm(Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
- if (!Val) return Fail;
+ if (!Val) return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
- return Success;
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
- if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder){
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
- CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
- if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
- if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
+ if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
- if (Rm == 0xF) CHECK(S, Unpredictable);
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
+ if (Rm == 0xF) S = MCDisassembler::SoftFail;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
- if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
- CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned index = 0;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
if (fieldFromInstruction32(Insn, 4, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 5, 3);
break;
case 1:
if (fieldFromInstruction32(Insn, 5, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 6, 2);
if (fieldFromInstruction32(Insn, 4, 1))
align = 2;
break;
case 2:
if (fieldFromInstruction32(Insn, 6, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 7, 1);
if (fieldFromInstruction32(Insn, 4, 2) != 0)
align = 4;
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned index = 0;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
if (fieldFromInstruction32(Insn, 4, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 5, 3);
break;
case 1:
if (fieldFromInstruction32(Insn, 5, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 6, 2);
if (fieldFromInstruction32(Insn, 4, 1))
align = 2;
break;
case 2:
if (fieldFromInstruction32(Insn, 6, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 7, 1);
if (fieldFromInstruction32(Insn, 4, 2) != 0)
align = 4;
}
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = 1;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
index = fieldFromInstruction32(Insn, 5, 3);
if (fieldFromInstruction32(Insn, 4, 1))
break;
case 2:
if (fieldFromInstruction32(Insn, 5, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 7, 1);
if (fieldFromInstruction32(Insn, 4, 1) != 0)
align = 8;
break;
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = 1;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
index = fieldFromInstruction32(Insn, 5, 3);
if (fieldFromInstruction32(Insn, 4, 1))
break;
case 2:
if (fieldFromInstruction32(Insn, 5, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 7, 1);
if (fieldFromInstruction32(Insn, 4, 1) != 0)
align = 8;
}
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = 1;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
if (fieldFromInstruction32(Insn, 4, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 5, 3);
break;
case 1:
if (fieldFromInstruction32(Insn, 4, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 6, 2);
if (fieldFromInstruction32(Insn, 5, 1))
inc = 2;
break;
case 2:
if (fieldFromInstruction32(Insn, 4, 2))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 7, 1);
if (fieldFromInstruction32(Insn, 6, 1))
inc = 2;
break;
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = 1;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
if (fieldFromInstruction32(Insn, 4, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 5, 3);
break;
case 1:
if (fieldFromInstruction32(Insn, 4, 1))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 6, 2);
if (fieldFromInstruction32(Insn, 5, 1))
inc = 2;
break;
case 2:
if (fieldFromInstruction32(Insn, 4, 2))
- return Fail; // UNDEFINED
+ return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction32(Insn, 7, 1);
if (fieldFromInstruction32(Insn, 6, 1))
inc = 2;
}
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = 1;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
if (fieldFromInstruction32(Insn, 4, 1))
align = 4;
break;
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned inc = 1;
switch (size) {
default:
- return Fail;
+ return MCDisassembler::Fail;
case 0:
if (fieldFromInstruction32(Insn, 4, 1))
align = 4;
}
if (Rm != 0xF) { // Writeback
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
}
- CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) {
- if (Rm != 0xD)
- CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
- else
+ if (Rm != 0xD) {
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ } else
Inst.addOperand(MCOperand::CreateReg(0));
}
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
- CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
return S;
static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
- CHECK(S, Unpredictable);
-
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ S = MCDisassembler::SoftFail;
+
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
- CHECK(S, Unpredictable);
-
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
- CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
- CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
- CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
+ S = MCDisassembler::SoftFail;
+
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
return S;
}
static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- DecodeStatus S = Success;
+ DecodeStatus S = MCDisassembler::Success;
unsigned pred = fieldFromInstruction16(Insn, 4, 4);
// The InstPrinter needs to have the low bit of the predicate in
// the mask operand to be able to print it properly.
if (pred == 0xF) {
pred = 0xE;
- CHECK(S, Unpredictable);
+ S = MCDisassembler::SoftFail;
}
if ((mask & 0xF) == 0) {
// the predicate.
mask &= 0x10;
mask |= 0x8;
- CHECK(S, Unpredictable);
+ S = MCDisassembler::SoftFail;
}
Inst.addOperand(MCOperand::CreateImm(pred));
Inst.addOperand(MCOperand::CreateImm(mask));
return S;
}
+
+static DecodeStatus
+DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned addr = fieldFromInstruction32(Insn, 0, 8);
+ unsigned W = fieldFromInstruction32(Insn, 21, 1);
+ unsigned U = fieldFromInstruction32(Insn, 23, 1);
+ unsigned P = fieldFromInstruction32(Insn, 24, 1);
+ bool writeback = (W == 1) | (P == 0);
+
+ addr |= (U << 8) | (Rn << 9);
+
+ if (writeback && (Rn == Rt || Rn == Rt2))
+ Check(S, MCDisassembler::SoftFail);
+ if (Rt == Rt2)
+ Check(S, MCDisassembler::SoftFail);
+
+ // Rt
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // Rt2
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // Writeback operand
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // addr
+ if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
+
+static DecodeStatus
+DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned addr = fieldFromInstruction32(Insn, 0, 8);
+ unsigned W = fieldFromInstruction32(Insn, 21, 1);
+ unsigned U = fieldFromInstruction32(Insn, 23, 1);
+ unsigned P = fieldFromInstruction32(Insn, 24, 1);
+ bool writeback = (W == 1) | (P == 0);
+
+ addr |= (U << 8) | (Rn << 9);
+
+ if (writeback && (Rn == Rt || Rn == Rt2))
+ Check(S, MCDisassembler::SoftFail);
+
+ // Writeback operand
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // Rt
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // Rt2
+ if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ // addr
+ if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
+
+static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
+ unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
+ if (sign1 != sign2) return MCDisassembler::Fail;
+
+ unsigned Val = fieldFromInstruction32(Insn, 0, 8);
+ Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
+ Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
+ Val |= sign1 << 12;
+ Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
+ uint64_t Address,
+ const void *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
+
+ // Shift of "asr #32" is not allowed in Thumb2 mode.
+ if (Val == 0x20) S = MCDisassembler::SoftFail;
+ Inst.addOperand(MCOperand::CreateImm(Val));
+ return S;
+}
+
+static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+ unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+
+ if (pred == 0xF)
+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
+
+ DecodeStatus S = MCDisassembler::Success;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+ return MCDisassembler::Fail;
+
+ return S;
+}
+
+static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
+ Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
+ unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
+ Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
+ unsigned imm = fieldFromInstruction32(Insn, 16, 6);
+ unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
+
+ DecodeStatus S = MCDisassembler::Success;
+
+ // VMOVv2f32 is ambiguous with these decodings.
+ if (!(imm & 0x38) && cmode == 0xF) {
+ Inst.setOpcode(ARM::VMOVv2f32);
+ return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
+ }
+
+ if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::CreateImm(64 - imm));
+
+ return S;
+}
+
+static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
+ Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
+ unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
+ Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
+ unsigned imm = fieldFromInstruction32(Insn, 16, 6);
+ unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
+
+ DecodeStatus S = MCDisassembler::Success;
+
+ // VMOVv4f32 is ambiguous with these decodings.
+ if (!(imm & 0x38) && cmode == 0xF) {
+ Inst.setOpcode(ARM::VMOVv4f32);
+ return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
+ }
+
+ if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
+
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::CreateImm(64 - imm));
+
+ return S;
+}
projects / oota-llvm.git / blobdiff