Be stricter in enforcing IT instruction predicate values, so that we don't end up...

[oota-llvm.git] / lib / Target / ARM / Disassembler / ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index c4b2f613cc7b8e65b2e465c85f6b59451be98b22..346bd2b04a4e5761112e355b616afc4c9e36b4ac 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -228,6 +228,8 @@ static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
                                 uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
+                                uint64_t Address, const void *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 #include "ARMGenInstrInfo.inc"
@@ -3289,3 +3291,15 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
   return S;
 }
 
+static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
+                                 uint64_t Address, const void *Decoder) {
+  DecodeStatus S = Success;
+  if (Cond == 0xF) {
+    Cond = 0xE;
+    CHECK(S, Unpredictable);
+  }
+
+  Inst.addOperand(MCOperand::CreateImm(Cond));
+  return S;
+}
+