#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmLexer.h"
#include "llvm/MC/MCAsmParser.h"
+#include "llvm/MC/MCParsedAsmOperand.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetAsmParser.h"
bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
- bool ParseRegister(ARMOperand &Op);
+ bool MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack);
bool ParseRegisterList(ARMOperand &Op);
bool ParseMemory(ARMOperand &Op);
- bool ParseShift(enum ShiftType *St, const MCExpr *&ShiftAmount);
+ bool ParseMemoryOffsetReg(bool &Negative,
+ bool &OffsetRegShifted,
+ enum ShiftType &ShiftType,
+ const MCExpr *&ShiftAmount,
+ const MCExpr *&Offset,
+ bool &OffsetIsReg,
+ int &OffsetRegNum);
+
+ bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount);
bool ParseOperand(ARMOperand &Op);
bool ParseDirectiveWord(unsigned Size, SMLoc L);
+ bool ParseDirectiveThumb(SMLoc L);
+
+ bool ParseDirectiveThumbFunc(SMLoc L);
+
+ bool ParseDirectiveCode(SMLoc L);
+
+ bool ParseDirectiveSyntax(SMLoc L);
+
// TODO - For now hacked versions of the next two are in here in this file to
// allow some parser testing until the table gen versions are implemented.
/// @name Auto-generated Match Functions
/// {
- bool MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
+ bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCInst &Inst);
/// MatchRegisterName - Match the given string to a register name and return
ARMAsmParser(const Target &T, MCAsmParser &_Parser)
: TargetAsmParser(T), Parser(_Parser) {}
- virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
+ virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
+ SmallVectorImpl<MCParsedAsmOperand*> &Operands);
virtual bool ParseDirective(AsmToken DirectiveID);
};
-} // end anonymous namespace
-
-namespace {
-
/// ARMOperand - Instances of this class represent a parsed ARM machine
/// instruction.
-struct ARMOperand {
+struct ARMOperand : public MCParsedAsmOperand {
enum {
Token,
Register,
+ Immediate,
Memory
} Kind;
bool Writeback;
} Reg;
+ struct {
+ const MCExpr *Val;
+ } Imm;
+
// This is for all forms of ARM address expressions
struct {
unsigned BaseRegNum;
- bool OffsetIsReg;
- const MCExpr *Offset; // used when OffsetIsReg is false
unsigned OffsetRegNum; // used when OffsetIsReg is true
- bool OffsetRegShifted; // only used when OffsetIsReg is true
- enum ShiftType ShiftType; // used when OffsetRegShifted is true
+ const MCExpr *Offset; // used when OffsetIsReg is false
const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
- bool Preindexed;
- bool Postindexed;
- bool Negative; // only used when OffsetIsReg is true
- bool Writeback;
+ enum ShiftType ShiftType; // used when OffsetRegShifted is true
+ unsigned
+ OffsetRegShifted : 1, // only used when OffsetIsReg is true
+ Preindexed : 1,
+ Postindexed : 1,
+ OffsetIsReg : 1,
+ Negative : 1, // only used when OffsetIsReg is true
+ Writeback : 1;
} Mem;
};
return Reg.RegNum;
}
+ const MCExpr *getImm() const {
+ assert(Kind == Immediate && "Invalid access!");
+ return Imm.Val;
+ }
+
bool isToken() const {return Kind == Token; }
bool isReg() const { return Kind == Register; }
return Res;
}
+ static ARMOperand CreateImm(const MCExpr *Val) {
+ ARMOperand Res;
+ Res.Kind = Immediate;
+ Res.Imm.Val = Val;
+ return Res;
+ }
+
static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
const MCExpr *Offset, unsigned OffsetRegNum,
bool OffsetRegShifted, enum ShiftType ShiftType,
} // end anonymous namespace.
-// Try to parse a register name. The token must be an Identifier when called,
-// and if it is a register name a Reg operand is created, the token is eaten
-// and false is returned. Else true is returned and no token is eaten.
-// TODO this is likely to change to allow different register types and or to
-// parse for a specific register type.
-bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
+/// Try to parse a register name. The token must be an Identifier when called,
+/// and if it is a register name a Reg operand is created, the token is eaten
+/// and false is returned. Else true is returned and no token is eaten.
+/// TODO this is likely to change to allow different register types and or to
+/// parse for a specific register type.
+bool ARMAsmParser::MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack) {
const AsmToken &Tok = getLexer().getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
getLexer().Lex(); // Eat identifier token.
bool Writeback = false;
- const AsmToken &ExclaimTok = getLexer().getTok();
- if (ExclaimTok.is(AsmToken::Exclaim)) {
- Writeback = true;
- getLexer().Lex(); // Eat exclaim token
+ if (ParseWriteBack) {
+ const AsmToken &ExclaimTok = getLexer().getTok();
+ if (ExclaimTok.is(AsmToken::Exclaim)) {
+ Writeback = true;
+ getLexer().Lex(); // Eat exclaim token
+ }
}
Op = ARMOperand::CreateReg(RegNum, Writeback);
return false;
}
-// Try to parse a register list. The first token must be a '{' when called
-// for now.
+/// Parse a register list, return false if successful else return true or an
+/// error. The first token must be a '{' when called.
bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
- const AsmToken &LCurlyTok = getLexer().getTok();
- assert(LCurlyTok.is(AsmToken::LCurly) && "Token is not an Left Curly Brace");
+ assert(getLexer().getTok().is(AsmToken::LCurly) &&
+ "Token is not an Left Curly Brace");
getLexer().Lex(); // Eat left curly brace token.
const AsmToken &RegTok = getLexer().getTok();
return false;
}
-// Try to parse an arm memory expression. It must start with a '[' token.
-// TODO Only preindexing and postindexing addressing are started, unindexed
-// with option, etc are still to do.
+/// Parse an arm memory expression, return false if successful else return true
+/// or an error. The first token must be a '[' when called.
+/// TODO Only preindexing and postindexing addressing are started, unindexed
+/// with option, etc are still to do.
bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
- const AsmToken &LBracTok = getLexer().getTok();
- assert(LBracTok.is(AsmToken::LBrac) && "Token is not an Left Bracket");
+ assert(getLexer().getTok().is(AsmToken::LBrac) &&
+ "Token is not an Left Bracket");
getLexer().Lex(); // Eat left bracket token.
const AsmToken &BaseRegTok = getLexer().getTok();
if (BaseRegTok.isNot(AsmToken::Identifier))
return Error(BaseRegTok.getLoc(), "register expected");
- int BaseRegNum = MatchRegisterName(BaseRegTok.getString());
- if (BaseRegNum == -1)
+ if (MaybeParseRegister(Op, false))
return Error(BaseRegTok.getLoc(), "register expected");
- getLexer().Lex(); // Eat identifier token.
+ int BaseRegNum = Op.getReg();
bool Preindexed = false;
bool Postindexed = false;
bool Negative = false;
bool Writeback = false;
- // First look for preindexed address forms:
- // [Rn, +/-Rm]
- // [Rn, #offset]
- // [Rn, +/-Rm, shift]
- // that is after the "[Rn" we now have see if the next token is a comma.
+ // First look for preindexed address forms, that is after the "[Rn" we now
+ // have to see if the next token is a comma.
const AsmToken &Tok = getLexer().getTok();
if (Tok.is(AsmToken::Comma)) {
Preindexed = true;
getLexer().Lex(); // Eat comma token.
-
- const AsmToken &NextTok = getLexer().getTok();
- if (NextTok.is(AsmToken::Plus))
- getLexer().Lex(); // Eat plus token.
- else if (NextTok.is(AsmToken::Minus)) {
- Negative = true;
- getLexer().Lex(); // Eat minus token
- }
-
- // See if there is a register following the "[Rn," we have so far.
- const AsmToken &OffsetRegTok = getLexer().getTok();
- int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
- bool OffsetRegShifted = false;
+ int OffsetRegNum;
+ bool OffsetRegShifted;
enum ShiftType ShiftType;
const MCExpr *ShiftAmount;
const MCExpr *Offset;
- if (OffsetRegNum != -1) {
- OffsetIsReg = true;
- getLexer().Lex(); // Eat identifier token for the offset register.
- // Look for a comma then a shift
- const AsmToken &Tok = getLexer().getTok();
- if (Tok.is(AsmToken::Comma)) {
- getLexer().Lex(); // Eat comma token.
-
- const AsmToken &Tok = getLexer().getTok();
- if (ParseShift(&ShiftType, ShiftAmount))
- return Error(Tok.getLoc(), "shift expected");
- OffsetRegShifted = true;
- }
- }
- else { // "[Rn," we have so far was not followed by "Rm"
- // Look for #offset following the "[Rn,"
- const AsmToken &HashTok = getLexer().getTok();
- if (HashTok.isNot(AsmToken::Hash))
- return Error(HashTok.getLoc(), "'#' expected");
- getLexer().Lex(); // Eat hash token.
-
- if (getParser().ParseExpression(Offset))
- return true;
- }
+ if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
+ Offset, OffsetIsReg, OffsetRegNum))
+ return true;
const AsmToken &RBracTok = getLexer().getTok();
if (RBracTok.isNot(AsmToken::RBrac))
return Error(RBracTok.getLoc(), "']' expected");
}
// The "[Rn" we have so far was not followed by a comma.
else if (Tok.is(AsmToken::RBrac)) {
- // This is a post indexing addressing forms:
- // [Rn], #offset
- // [Rn], +/-Rm
- // [Rn], +/-Rm, shift
- // that is a ']' follows after the "[Rn".
+ // This is a post indexing addressing forms, that is a ']' follows after
+ // the "[Rn".
Postindexed = true;
Writeback = true;
getLexer().Lex(); // Eat right bracket token.
- const AsmToken &CommaTok = getLexer().getTok();
- if (CommaTok.isNot(AsmToken::Comma))
- return Error(CommaTok.getLoc(), "',' expected");
- getLexer().Lex(); // Eat comma token.
-
- const AsmToken &NextTok = getLexer().getTok();
- if (NextTok.is(AsmToken::Plus))
- getLexer().Lex(); // Eat plus token.
- else if (NextTok.is(AsmToken::Minus)) {
- Negative = true;
- getLexer().Lex(); // Eat minus token
- }
-
- // See if there is a register following the "[Rn]," we have so far.
- const AsmToken &OffsetRegTok = getLexer().getTok();
- int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
+ int OffsetRegNum = 0;
bool OffsetRegShifted = false;
enum ShiftType ShiftType;
const MCExpr *ShiftAmount;
const MCExpr *Offset;
- if (OffsetRegNum != -1) {
- OffsetIsReg = true;
- getLexer().Lex(); // Eat identifier token for the offset register.
- // Look for a comma then a shift
- const AsmToken &Tok = getLexer().getTok();
- if (Tok.is(AsmToken::Comma)) {
- getLexer().Lex(); // Eat comma token.
-
- const AsmToken &Tok = getLexer().getTok();
- if (ParseShift(&ShiftType, ShiftAmount))
- return Error(Tok.getLoc(), "shift expected");
- OffsetRegShifted = true;
- }
- }
- else { // "[Rn]," we have so far was not followed by "Rm"
- // Look for #offset following the "[Rn],"
- const AsmToken &HashTok = getLexer().getTok();
- if (HashTok.isNot(AsmToken::Hash))
- return Error(HashTok.getLoc(), "'#' expected");
- getLexer().Lex(); // Eat hash token.
-
- if (getParser().ParseExpression(Offset))
- return true;
+
+ const AsmToken &NextTok = getLexer().getTok();
+ if (NextTok.isNot(AsmToken::EndOfStatement)) {
+ if (NextTok.isNot(AsmToken::Comma))
+ return Error(NextTok.getLoc(), "',' expected");
+ getLexer().Lex(); // Eat comma token.
+ if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
+ ShiftAmount, Offset, OffsetIsReg, OffsetRegNum))
+ return true;
}
+
Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
OffsetRegShifted, ShiftType, ShiftAmount,
Preindexed, Postindexed, Negative, Writeback);
return true;
}
+/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
+/// we will parse the following (were +/- means that a plus or minus is
+/// optional):
+/// +/-Rm
+/// +/-Rm, shift
+/// #offset
+/// we return false on success or an error otherwise.
+bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
+ bool &OffsetRegShifted,
+ enum ShiftType &ShiftType,
+ const MCExpr *&ShiftAmount,
+ const MCExpr *&Offset,
+ bool &OffsetIsReg,
+ int &OffsetRegNum) {
+ ARMOperand Op;
+ Negative = false;
+ OffsetRegShifted = false;
+ OffsetIsReg = false;
+ OffsetRegNum = -1;
+ const AsmToken &NextTok = getLexer().getTok();
+ if (NextTok.is(AsmToken::Plus))
+ getLexer().Lex(); // Eat plus token.
+ else if (NextTok.is(AsmToken::Minus)) {
+ Negative = true;
+ getLexer().Lex(); // Eat minus token
+ }
+ // See if there is a register following the "[Rn," or "[Rn]," we have so far.
+ const AsmToken &OffsetRegTok = getLexer().getTok();
+ if (OffsetRegTok.is(AsmToken::Identifier)) {
+ OffsetIsReg = !MaybeParseRegister(Op, false);
+ if (OffsetIsReg)
+ OffsetRegNum = Op.getReg();
+ }
+ // If we parsed a register as the offset then their can be a shift after that
+ if (OffsetRegNum != -1) {
+ // Look for a comma then a shift
+ const AsmToken &Tok = getLexer().getTok();
+ if (Tok.is(AsmToken::Comma)) {
+ getLexer().Lex(); // Eat comma token.
+
+ const AsmToken &Tok = getLexer().getTok();
+ if (ParseShift(ShiftType, ShiftAmount))
+ return Error(Tok.getLoc(), "shift expected");
+ OffsetRegShifted = true;
+ }
+ }
+ else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
+ // Look for #offset following the "[Rn," or "[Rn],"
+ const AsmToken &HashTok = getLexer().getTok();
+ if (HashTok.isNot(AsmToken::Hash))
+ return Error(HashTok.getLoc(), "'#' expected");
+ getLexer().Lex(); // Eat hash token.
+
+ if (getParser().ParseExpression(Offset))
+ return true;
+ }
+ return false;
+}
+
/// ParseShift as one of these two:
/// ( lsl | lsr | asr | ror ) , # shift_amount
/// rrx
/// and returns true if it parses a shift otherwise it returns false.
-bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *&ShiftAmount) {
+bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount) {
const AsmToken &Tok = getLexer().getTok();
if (Tok.isNot(AsmToken::Identifier))
return true;
const StringRef &ShiftName = Tok.getString();
if (ShiftName == "lsl" || ShiftName == "LSL")
- *St = Lsl;
+ St = Lsl;
else if (ShiftName == "lsr" || ShiftName == "LSR")
- *St = Lsr;
+ St = Lsr;
else if (ShiftName == "asr" || ShiftName == "ASR")
- *St = Asr;
+ St = Asr;
else if (ShiftName == "ror" || ShiftName == "ROR")
- *St = Ror;
+ St = Ror;
else if (ShiftName == "rrx" || ShiftName == "RRX")
- *St = Rrx;
+ St = Rrx;
else
return true;
getLexer().Lex(); // Eat shift type token.
- // For all but a Rotate right there must be a '#' and a shift amount
- if (*St != Rrx) {
- // Look for # following the shift type
- const AsmToken &HashTok = getLexer().getTok();
- if (HashTok.isNot(AsmToken::Hash))
- return Error(HashTok.getLoc(), "'#' expected");
- getLexer().Lex(); // Eat hash token.
+ // Rrx stands alone.
+ if (St == Rrx)
+ return false;
- if (getParser().ParseExpression(ShiftAmount))
- return true;
- }
+ // Otherwise, there must be a '#' and a shift amount.
+ const AsmToken &HashTok = getLexer().getTok();
+ if (HashTok.isNot(AsmToken::Hash))
+ return Error(HashTok.getLoc(), "'#' expected");
+ getLexer().Lex(); // Eat hash token.
+
+ if (getParser().ParseExpression(ShiftAmount))
+ return true;
return false;
}
-// A hack to allow some testing
+/// A hack to allow some testing, to be replaced by a real table gen version.
int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
if (Name == "r0" || Name == "R0")
return 0;
return -1;
}
-// A hack to allow some testing
-bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
- MCInst &Inst) {
- struct ARMOperand Op0 = Operands[0];
+/// A hack to allow some testing, to be replaced by a real table gen version.
+bool ARMAsmParser::
+MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
+ MCInst &Inst) {
+ ARMOperand &Op0 = *(ARMOperand*)Operands[0];
assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
const StringRef &Mnemonic = Op0.getToken();
if (Mnemonic == "add" ||
Mnemonic == "str" ||
Mnemonic == "ldmfd" ||
Mnemonic == "ldr" ||
- Mnemonic == "mov")
+ Mnemonic == "mov" ||
+ Mnemonic == "sub" ||
+ Mnemonic == "bl" ||
+ Mnemonic == "push" ||
+ Mnemonic == "blx" ||
+ Mnemonic == "pop") {
+ // Hard-coded to a valid instruction, till we have a real matcher.
+ Inst = MCInst();
+ Inst.setOpcode(ARM::MOVr);
+ Inst.addOperand(MCOperand::CreateReg(2));
+ Inst.addOperand(MCOperand::CreateReg(2));
+ Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::CreateReg(0));
return false;
+ }
return true;
}
-// TODO - this is a work in progress
+/// Parse a arm instruction operand. For now this parses the operand regardless
+/// of the mnemonic.
bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
switch (getLexer().getKind()) {
case AsmToken::Identifier:
- if (!ParseRegister(Op))
+ if (!MaybeParseRegister(Op, true))
return false;
- // TODO parse other operands that start with an identifier like labels
- return Error(getLexer().getTok().getLoc(), "labels not yet supported");
+ // This was not a register so parse other operands that start with an
+ // identifier (like labels) as expressions and create them as immediates.
+ const MCExpr *IdVal;
+ if (getParser().ParseExpression(IdVal))
+ return true;
+ Op = ARMOperand::CreateImm(IdVal);
+ return false;
case AsmToken::LBrac:
- if (!ParseMemory(Op))
- return false;
+ return ParseMemory(Op);
case AsmToken::LCurly:
- if (!ParseRegisterList(Op))
- return(false);
+ return ParseRegisterList(Op);
case AsmToken::Hash:
- return Error(getLexer().getTok().getLoc(), "immediates not yet supported");
+ // #42 -> immediate.
+ // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
+ getLexer().Lex();
+ const MCExpr *ImmVal;
+ if (getParser().ParseExpression(ImmVal))
+ return true;
+ Op = ARMOperand::CreateImm(ImmVal);
+ return false;
default:
return Error(getLexer().getTok().getLoc(), "unexpected token in operand");
}
}
-bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
- SmallVector<ARMOperand, 7> Operands;
-
- Operands.push_back(ARMOperand::CreateToken(Name));
+/// Parse an arm instruction mnemonic followed by its operands.
+bool ARMAsmParser::ParseInstruction(const StringRef &Name, SMLoc NameLoc,
+ SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ Operands.push_back(new ARMOperand(ARMOperand::CreateToken(Name)));
SMLoc Loc = getLexer().getTok().getLoc();
if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand.
- Operands.push_back(ARMOperand());
- if (ParseOperand(Operands.back()))
- return true;
+ ARMOperand Op;
+ if (ParseOperand(Op)) return true;
+ Operands.push_back(new ARMOperand(Op));
while (getLexer().is(AsmToken::Comma)) {
getLexer().Lex(); // Eat the comma.
// Parse and remember the operand.
- Operands.push_back(ARMOperand());
- if (ParseOperand(Operands.back()))
- return true;
+ if (ParseOperand(Op)) return true;
+ Operands.push_back(new ARMOperand(Op));
}
}
- if (!MatchInstruction(Operands, Inst))
- return false;
-
- Error(Loc, "ARMAsmParser::ParseInstruction only partly implemented");
- return true;
+ return false;
}
+/// ParseDirective parses the arm specific directives
bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
return ParseDirectiveWord(4, DirectiveID.getLoc());
+ else if (IDVal == ".thumb")
+ return ParseDirectiveThumb(DirectiveID.getLoc());
+ else if (IDVal == ".thumb_func")
+ return ParseDirectiveThumbFunc(DirectiveID.getLoc());
+ else if (IDVal == ".code")
+ return ParseDirectiveCode(DirectiveID.getLoc());
+ else if (IDVal == ".syntax")
+ return ParseDirectiveSyntax(DirectiveID.getLoc());
return true;
}
return false;
}
-// Force static initialization.
+/// ParseDirectiveThumb
+/// ::= .thumb
+bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(L, "unexpected token in directive");
+ getLexer().Lex();
+
+ // TODO: set thumb mode
+ // TODO: tell the MC streamer the mode
+ // getParser().getStreamer().Emit???();
+ return false;
+}
+
+/// ParseDirectiveThumbFunc
+/// ::= .thumbfunc symbol_name
+bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
+ const AsmToken &Tok = getLexer().getTok();
+ if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
+ return Error(L, "unexpected token in .syntax directive");
+ StringRef ATTRIBUTE_UNUSED SymbolName = getLexer().getTok().getIdentifier();
+ getLexer().Lex(); // Consume the identifier token.
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(L, "unexpected token in directive");
+ getLexer().Lex();
+
+ // TODO: mark symbol as a thumb symbol
+ // getParser().getStreamer().Emit???();
+ return false;
+}
+
+/// ParseDirectiveSyntax
+/// ::= .syntax unified | divided
+bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
+ const AsmToken &Tok = getLexer().getTok();
+ if (Tok.isNot(AsmToken::Identifier))
+ return Error(L, "unexpected token in .syntax directive");
+ const StringRef &Mode = Tok.getString();
+ bool unified_syntax;
+ if (Mode == "unified" || Mode == "UNIFIED") {
+ getLexer().Lex();
+ unified_syntax = true;
+ }
+ else if (Mode == "divided" || Mode == "DIVIDED") {
+ getLexer().Lex();
+ unified_syntax = false;
+ }
+ else
+ return Error(L, "unrecognized syntax mode in .syntax directive");
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(getLexer().getTok().getLoc(), "unexpected token in directive");
+ getLexer().Lex();
+
+ // TODO tell the MC streamer the mode
+ // getParser().getStreamer().Emit???();
+ return false;
+}
+
+/// ParseDirectiveCode
+/// ::= .code 16 | 32
+bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
+ const AsmToken &Tok = getLexer().getTok();
+ if (Tok.isNot(AsmToken::Integer))
+ return Error(L, "unexpected token in .code directive");
+ int64_t Val = getLexer().getTok().getIntVal();
+ bool thumb_mode;
+ if (Val == 16) {
+ getLexer().Lex();
+ thumb_mode = true;
+ }
+ else if (Val == 32) {
+ getLexer().Lex();
+ thumb_mode = false;
+ }
+ else
+ return Error(L, "invalid operand to .code directive");
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(getLexer().getTok().getLoc(), "unexpected token in directive");
+ getLexer().Lex();
+
+ // TODO tell the MC streamer the mode
+ // getParser().getStreamer().Emit???();
+ return false;
+}
+
+/// Force static initialization.
extern "C" void LLVMInitializeARMAsmParser() {
RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
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