return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
Val == INT32_MIN;
}
- bool isAddrMode5FP16() const {
- // If we have an immediate that's not a constant, treat it as a label
- // reference needing a fixup. If it is a constant, it's something else
- // and we reject it.
- if (isImm() && !isa<MCConstantExpr>(getImm()))
- return true;
- if (!isMem() || Memory.Alignment != 0) return false;
- // Check for register offset.
- if (Memory.OffsetRegNum) return false;
- // Immediate offset in range [-510, 510] and a multiple of 2.
- if (!Memory.OffsetImm) return true;
- int64_t Val = Memory.OffsetImm->getValue();
- return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
- }
bool isMemTBB() const {
if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
Inst.addOperand(MCOperand::createImm(Val));
}
- void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
- assert(N == 2 && "Invalid number of operands!");
- // If we have an immediate that's not a constant, treat it as a label
- // reference needing a fixup. If it is a constant, it's something else
- // and we reject it.
- if (isImm()) {
- Inst.addOperand(MCOperand::createExpr(getImm()));
- Inst.addOperand(MCOperand::createImm(0));
- return;
- }
-
- // The lower bit is always zero and as such is not encoded.
- int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
- ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
- // Special case for #-0
- if (Val == INT32_MIN) Val = 0;
- if (Val < 0) Val = -Val;
- Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
- Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
- Inst.addOperand(MCOperand::createImm(Val));
- }
-
void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
// If we have an immediate that's not a constant, treat it as a label
// vmov.i{8|16|32|64} <dreg|qreg>, #imm
ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
bool isVmovf = TyOp.isToken() &&
- (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
- TyOp.getToken() == ".f16");
+ (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
Mnemonic.getToken() == "fconsts");
Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
- Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx")
+ Mnemonic.startswith("vsel"))
return Mnemonic;
// First, split out any predication code. Ignore mnemonics we know aren't
Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
- (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
- Mnemonic == "vmovx" || Mnemonic == "vins") {
+ (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
// These mnemonics are never predicable
CanAcceptPredicationCode = false;
} else if (!isThumb()) {