More pseudo instruction scheduling itinerary fixes.

[oota-llvm.git] / lib / Target / ARM / ARMScheduleV6.td

diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td
index b382a7a51912a960c93e14406a10e537514c2773..52d2dc1e494aec751820b162b96ec166d828fe8c 100644 (file)
--- a/lib/Target/ARM/ARMScheduleV6.td
+++ b/lib/Target/ARM/ARMScheduleV6.td
@@ -46,6 +46,8 @@ def ARMV6Itineraries : ProcessorItineraries<
   InstrItinData<IIC_iMOVr    , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
   InstrItinData<IIC_iMOVsi   , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
   InstrItinData<IIC_iMOVsr   , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
+  InstrItinData<IIC_iMOVix2  , [InstrStage<1, [V6_Pipe]>,
+                                InstrStage<1, [V6_Pipe]>], [2]>,
   //
   // Move instructions, conditional
   InstrItinData<IIC_iCMOVi   , [InstrStage<1, [V6_Pipe]>], [3]>,
@@ -91,6 +93,11 @@ def ARMV6Itineraries : ProcessorItineraries<
   InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>,
                                 InstrStage<1, [V6_Pipe]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
+                                InstrStage<1, [V6_Pipe]>], [3, 1]>,
+
   // Integer store pipeline
   //
   // Immediate offset