[ARM] Mark Swift MISched model as incomplete

[oota-llvm.git] / lib / Target / ARM / ARMScheduleSwift.td

diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td
index 6f5740fd13052cc01df62099d5ae8659dd5ad854..3ad7730228e5fb8753bba8d9670134c4468d5dd6 100644 (file)
--- a/lib/Target/ARM/ARMScheduleSwift.td
+++ b/lib/Target/ARM/ARMScheduleSwift.td
@@ -43,6 +43,7 @@ def SwiftModel : SchedMachineModel {
   let MicroOpBufferSize = 45; // Based on NEON renamed registers.
   let LoadLatency = 3;
   let MispredictPenalty = 14; // A branch direction mispredict.
+  let CompleteModel = 0;      // FIXME: Remove if all instructions are covered.
 }
 
 // Swift predicates.