More pseudo instruction scheduling itinerary fixes.

[oota-llvm.git] / lib / Target / ARM / ARMScheduleA9.td

diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td
index b37b3948f1711fc900ec5d67fed5804e6c19e094..a4be5a73746b515e657d483be87a1bb25d07649a 100644 (file)
--- a/lib/Target/ARM/ARMScheduleA9.td
+++ b/lib/Target/ARM/ARMScheduleA9.td
@@ -33,7 +33,7 @@ def CortexA9Itineraries : ProcessorItineraries<
   // Move instructions, unconditional
   InstrItinData<IIC_iMOVi   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
   InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
-                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
+                               InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
   InstrItinData<IIC_iMOVr   , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
   InstrItinData<IIC_iMOVsr  , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
@@ -115,6 +115,12 @@ def CortexA9Itineraries : ProcessorItineraries<
                                 InstrStage<1, [A9_LSPipe]>,
                                 InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
 
+  //
+  // iLoadi + iALUr for t2LDRpci_pic.
+  InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Pipe1]>,
+                                InstrStage<1, [A9_LSPipe]>,
+                                InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [4, 1]>,
+
   // Integer store pipeline
   ///
   // Immediate offset