Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."

[oota-llvm.git] / lib / Target / ARM / ARMScheduleA8.td

diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td
index 61de00a2086af3227e1dede9f279910713a57dde..eb1083ca23f3a2329242e7747e8d06ae43674775 100644 (file)
--- a/lib/Target/ARM/ARMScheduleA8.td
+++ b/lib/Target/ARM/ARMScheduleA8.td
@@ -155,30 +155,28 @@ def CortexA8Itineraries : MultiIssueItineraries<
   // Load multiple, def is the 5th operand. Pipeline 0 only.
   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
   InstrItinData<IIC_iLoad_m  , [InstrStage<2, [A8_Pipe0], 0>,
-                                InstrStage<2, [A8_LSPipe]>],
-                [1, 1, 1, 1, 3], [], -1>, // dynamic uops
+                                InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
   //
   // Load multiple + update, defs are the 1st and 5th operands.
   InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>,
-                                InstrStage<3, [A8_LSPipe]>],
-                [2, 1, 1, 1, 3], [], -1>, // dynamic uops
+                                InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
   //
   // Load multiple plus branch
   InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>,
                                 InstrStage<3, [A8_LSPipe]>,
                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
-                              [1, 2, 1, 1, 3], [], -1>, // dynamic uops
+                               [1, 2, 1, 1, 3]>,
   //
   // Pop, def is the 3rd operand.
   InstrItinData<IIC_iPop  ,    [InstrStage<3, [A8_Pipe0], 0>,
-                                InstrStage<3, [A8_LSPipe]>],
-                [1, 1, 3], [], -1>, // dynamic uops
+                                InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
   //
   // Push, def is the 3th operand.
   InstrItinData<IIC_iPop_Br,   [InstrStage<3, [A8_Pipe0], 0>,
                                 InstrStage<3, [A8_LSPipe]>,
                                 InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
-                               [1, 1, 3], [], -1>, // dynamic uops
+                               [1, 1, 3]>,
+
   //
   // iLoadi + iALUr for t2LDRpci_pic.
   InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
@@ -233,13 +231,12 @@ def CortexA8Itineraries : MultiIssueItineraries<
   // Store multiple. Pipeline 0 only.
   // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
   InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>,
-                                InstrStage<2, [A8_LSPipe]>],
-                [], [], -1>, // dynamic uops
+                                InstrStage<2, [A8_LSPipe]>]>,
   //
   // Store multiple + update
   InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>,
-                                InstrStage<2, [A8_LSPipe]>],
-                [2], [], -1>, // dynamic uops
+                                InstrStage<2, [A8_LSPipe]>], [2]>,
+
   //
   // Preload
   InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,
@@ -400,16 +397,14 @@ def CortexA8Itineraries : MultiIssueItineraries<
                                InstrStage<1, [A8_NLSPipe], 0>,
                                InstrStage<1, [A8_LSPipe]>,
                                InstrStage<1, [A8_NLSPipe], 0>,
-                               InstrStage<1, [A8_LSPipe]>],
-                [1, 1, 1, 2], [], -1>, // dynamic uops
+                               InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
   //
   // FP Load Multiple + update
   InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
                                InstrStage<1, [A8_NLSPipe], 0>,
                                InstrStage<1, [A8_LSPipe]>,
                                InstrStage<1, [A8_NLSPipe], 0>,
-                               InstrStage<1, [A8_LSPipe]>],
-                [2, 1, 1, 1, 2], [], -1>, // dynamic uops
+                               InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
   //
   // Single-precision FP Store
   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
@@ -428,16 +423,15 @@ def CortexA8Itineraries : MultiIssueItineraries<
                                InstrStage<1, [A8_NLSPipe], 0>,
                                InstrStage<1, [A8_LSPipe]>,
                                InstrStage<1, [A8_NLSPipe], 0>,
-                               InstrStage<1, [A8_LSPipe]>],
-                [1, 1, 1, 1], [], -1>, // dynamic uops
+                               InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
   //
   // FP Store Multiple + update
   InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
                                 InstrStage<1, [A8_NLSPipe], 0>,
                                 InstrStage<1, [A8_LSPipe]>,
                                 InstrStage<1, [A8_NLSPipe], 0>,
-                                InstrStage<1, [A8_LSPipe]>],
-                [2, 1, 1, 1, 1], [], -1>, // dynamic uops
+                                InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
+
   // NEON
   // Issue through integer pipeline, and execute in NEON unit.
   //