ARM scheduler model: Swift has varying latencies, uops for simple ALU ops

[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 7eb5ff665a6efe8bf17213ea59f6063df6655f8a..136a90aa95cea5be7eb600be041b8771ca4b3225 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -71,6 +71,8 @@ def : PredicateProlog<[{
   (void)TII;
 }]>;
 
+def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //