Revert ARM Scheduler Model: Add resources instructions, map resources

[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 1bca55446e9b02f1f396b252ce682756e6f1cc15..ff1ff2fccf0ffbd3d380d6eaf2b706811bd97dc4 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -64,13 +64,6 @@ def WriteALUsr : SchedWrite; // Shift by register.
 def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
 def ReadAdvanceALUsr : SchedRead; // Some operands are read later.
 
-// Define TII for use in SchedVariant Predicates.
-def : PredicateProlog<[{
-  const ARMBaseInstrInfo *TII =
-    static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
-  (void)TII;
-}]>;
-
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //