Revert series of sched model patches until I figure out what is going on.

[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index f25e9c2e2a329ae210d67e945fbe19623d129c00..2d088de96e273d813b60680249c2a6b9e40d2b99 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -69,21 +69,6 @@ def WriteCMP : SchedWrite;
 def WriteCMPsi : SchedWrite;
 def WriteCMPsr : SchedWrite;
 
-// Division.
-def WriteDiv : SchedWrite;
-
-// Loads.
-def WriteLd : SchedWrite;
-def WritePreLd : SchedWrite;
-
-// Branches.
-def WriteBr : SchedWrite;
-def WriteBrL : SchedWrite;
-def WriteBrTbl : SchedWrite;
-
-// Fixpoint conversions.
-def WriteCvtFP : SchedWrite;
-
 // Define TII for use in SchedVariant Predicates.
 def : PredicateProlog<[{
   const ARMBaseInstrInfo *TII =