Add correct encodings for the rest of the vld instructions that we generate.

[oota-llvm.git] / lib / Target / ARM / ARMMCCodeEmitter.cpp

diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 6f32ce7645dfbc67aca1550d16f6b551046eb239..b3dce29e5c891d4c45c3203a12e8b6a7d1b73e1d 100644 (file)
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -100,6 +100,7 @@ public:
 
   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
   unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const;
+  unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const;
 
   unsigned getNumFixupKinds() const {
     assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
@@ -304,7 +305,7 @@ unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
   unsigned Align = Imm.getImm();
   switch(Align) {
-    case 8:  Align = 0x01; break;
+    case 2: case 4: case 8:  Align = 0x01; break;
     case 16: Align = 0x02; break;
     case 32: Align = 0x03; break;
     default: Align = 0x00; break;
@@ -312,6 +313,14 @@ unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
   return RegNo | (Align << 4);
 }
 
+unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI,
+                                                     unsigned Op) const {
+  const MCOperand &regno = MI.getOperand(Op);
+  if (regno.getReg() == 0) return 0x0D;
+  return regno.getReg();
+}
+
+
 void ARMMCCodeEmitter::
 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups) const {