The MC code couldn't handle ARM LDR instructions with negative offsets:

[oota-llvm.git] / lib / Target / ARM / ARMInstrVFP.td

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 4cf139ea9657a7bdf11b396662f46fa513fd166e..65f640ecd1f3c048efe77d381cd34503fc246bc9 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -51,25 +51,38 @@ def vfp_f64imm : Operand<f64>,
 //
 
 let canFoldAsLoad = 1, isReMaterializable = 1 in {
+
 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
                  IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
                  [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> {
   // Instruction operands.
-  bits<5> Dd;
-  bits<32> addr;
+  bits<5>  Dd;
+  bits<13> addr;
 
   // Encode instruction operands.
-  let Inst{23}    = addr{16};     // U (add = (U == '1'))
+  let Inst{23}    = addr{8};      // U (add = (U == '1'))
   let Inst{22}    = Dd{4};
-  let Inst{19-16} = addr{20-17};  // Rn
+  let Inst{19-16} = addr{12-9};   // Rn
   let Inst{15-12} = Dd{3-0};
   let Inst{7-0}   = addr{7-0};    // imm8
 }
 
-def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
-                 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
-                 [(set SPR:$dst, (load addrmode5:$addr))]>;
-} // canFoldAsLoad
+def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
+                 IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
+                 [(set SPR:$Sd, (load addrmode5:$addr))]> {
+  // Instruction operands.
+  bits<5>  Sd;
+  bits<13> addr;
+
+  // Encode instruction operands.
+  let Inst{23}    = addr{8};      // U (add = (U == '1'))
+  let Inst{22}    = Sd{0};
+  let Inst{19-16} = addr{12-9};   // Rn
+  let Inst{15-12} = Sd{4-1};
+  let Inst{7-0}   = addr{7-0};    // imm8
+}
+
+} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
 
 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
                  IIC_fpStore64, "vstr", ".64\t$src, $addr",