Add ARMv6 memory and sync barrier instructions

[oota-llvm.git] / lib / Target / ARM / ARMInstrThumb2.td

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index a2aa1c03e937afb09b893d9b2505ce2f41e4a780..949ce73c24a37f8e84a51e7a7b57cb25feb33002 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1073,7 +1073,7 @@ let hasSideEffects = 1 in {
 def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
-                        [(ARMMemBarrier)]>,
+                        [(ARMMemBarrierV7)]>,
                         Requires<[IsThumb2]> {
   // FIXME: add support for options other than a full system DMB
 }
@@ -1081,7 +1081,7 @@ def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
 def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
-                        [(ARMSyncBarrier)]>,
+                        [(ARMSyncBarrierV7)]>,
                         Requires<[IsThumb2]> {
   // FIXME: add support for options other than a full system DSB
 }