// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
def t2addrmode_imm8s4 : Operand<i32> {
let PrintMethod = "printT2AddrModeImm8s4Operand";
+ string EncoderMethod = "getT2AddrModeImm8s4OpValue";
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
bits<4> Rd;
bits<12> imm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
bits<4> Rn;
bits<12> imm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
bits<4> Rn;
bits<12> imm;
- let Inst{19-16} = Rn{3-0};
+ let Inst{19-16} = Rn;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
bits<4> Rd;
bits<12> ShiftedRm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
- : T2I<oops, iops, itin, opc, asm, pattern> {
+ : T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<12> ShiftedRm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
bits<4> Rn;
bits<12> ShiftedRm;
- let Inst{19-16} = Rn{3-0};
+ let Inst{19-16} = Rn;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
bits<4> Rd;
bits<4> Rm;
- let Inst{11-8} = Rd{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{3-0} = Rm;
}
class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
bits<4> Rd;
bits<4> Rm;
- let Inst{11-8} = Rd{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{3-0} = Rm;
}
class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
bits<4> Rn;
bits<4> Rm;
- let Inst{19-16} = Rn{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{19-16} = Rn;
+ let Inst{3-0} = Rm;
}
bits<4> Rd;
bits<4> Rm;
- let Inst{11-8} = Rd{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{3-0} = Rm;
}
class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
bits<4> Rn;
bits<12> imm;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
bits<4> Rm;
bits<5> imm;
- let Inst{11-8} = Rd{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{3-0} = Rm;
let Inst{14-12} = imm{4-2};
let Inst{7-6} = imm{1-0};
}
bits<4> Rm;
bits<5> imm;
- let Inst{11-8} = Rd{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{3-0} = Rm;
let Inst{14-12} = imm{4-2};
let Inst{7-6} = imm{1-0};
}
bits<4> Rn;
bits<4> Rm;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
+ let Inst{3-0} = Rm;
}
class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
bits<4> Rn;
bits<4> Rm;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
+ let Inst{3-0} = Rm;
}
class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
bits<4> Rn;
bits<12> ShiftedRm;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
bits<4> Rn;
bits<12> ShiftedRm;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
bits<4> Rm;
bits<4> Ra;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
- let Inst{3-0} = Rm{3-0};
- let Inst{15-12} = Ra{3-0};
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Ra;
+ let Inst{11-8} = Rd;
+ let Inst{3-0} = Rm;
+}
+
+class T2MulLong<dag oops, dag iops, InstrItinClass itin,
+ string opc, string asm, list<dag> pattern>
+ : T2I<oops, iops, itin, opc, asm, pattern> {
+ bits<4> RdLo;
+ bits<4> RdHi;
+ bits<4> Rn;
+ bits<4> Rm;
+
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = RdLo;
+ let Inst{11-8} = RdHi;
+ let Inst{3-0} = Rm;
}
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0;
}
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1111; // Rn
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1111; // Rn
}
}
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{15} = 0;
}
// register
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
}
}
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{15} = 0;
}
// register
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = ?; // The S bit.
}
}
let Inst{25} = 0;
let Inst{24} = 1;
let Inst{23-21} = op23_21;
- let Inst{20} = 0; // The S bit.
let Inst{15} = 0;
}
}
let Inst{26-25} = 0b01;
let Inst{24} = 1;
let Inst{23-21} = op23_21;
- let Inst{20} = 0; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
let Inst{26-25} = 0b01;
let Inst{24} = 1;
let Inst{23-21} = op23_21;
- let Inst{20} = 0; // The S bit.
}
}
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
- let Inst{20} = 0; // The S bit.
let Inst{15} = 0;
}
// register
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = 0; // The S bit.
let Inst{14-12} = 0b000; // imm3
let Inst{7-6} = 0b00; // imm2
let Inst{5-4} = 0b00; // type
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
- let Inst{20} = 0; // The S bit.
}
}
let Inst{23} = 1;
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
-
+
bits<4> Rt;
- let Inst{15-12} = Rt{3-0};
-
+ let Inst{15-12} = Rt;
+
bits<17> addr;
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
// Offset: index==TRUE, wback==FALSE
let Inst{10} = 1; // The P bit.
let Inst{8} = 0; // The W bit.
-
+
bits<4> Rt;
- let Inst{15-12} = Rt{3-0};
-
+ let Inst{15-12} = Rt;
+
bits<13> addr;
let Inst{19-16} = addr{12-9}; // Rn
let Inst{9} = addr{8}; // U
let Inst{22-21} = opcod;
let Inst{20} = 1; // load
let Inst{11-6} = 0b000000;
-
+
bits<4> Rt;
- let Inst{15-12} = Rt{3-0};
-
+ let Inst{15-12} = Rt;
+
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
let Inst{5-4} = addr{1-0}; // imm
}
- // FIXME: Is the pci variant actually needed?
- def pci : T2Ipc <(outs GPR:$Rt), (ins i32imm:$addr), iii,
- opc, ".w\t$Rt, $addr",
- [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
- let isReMaterializable = 1;
- let Inst{31-27} = 0b11111;
- let Inst{26-25} = 0b00;
- let Inst{24} = signed;
- let Inst{23} = ?; // add = (U == '1')
- let Inst{22-21} = opcod;
- let Inst{20} = 1; // load
- let Inst{19-16} = 0b1111; // Rn
-
- bits<4> Rt;
- bits<12> addr;
- let Inst{15-12} = Rt{3-0};
- let Inst{11-0} = addr{11-0};
- }
+ def pci : tPseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
+ [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>;
}
/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
let Inst{26-23} = 0b0001;
let Inst{22-21} = opcod;
let Inst{20} = 0; // !load
-
+
bits<4> Rt;
- let Inst{15-12} = Rt{3-0};
-
+ let Inst{15-12} = Rt;
+
bits<17> addr;
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
// Offset: index==TRUE, wback==FALSE
let Inst{10} = 1; // The P bit.
let Inst{8} = 0; // The W bit.
-
+
bits<4> Rt;
- let Inst{15-12} = Rt{3-0};
-
+ let Inst{15-12} = Rt;
+
bits<13> addr;
let Inst{19-16} = addr{12-9}; // Rn
let Inst{9} = addr{8}; // U
let Inst{22-21} = opcod;
let Inst{20} = 0; // !load
let Inst{11-6} = 0b000000;
-
+
bits<4> Rt;
- let Inst{15-12} = Rt{3-0};
-
+ let Inst{15-12} = Rt;
+
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
bits<4> Rd;
bits<12> label;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{26} = label{11};
let Inst{14-12} = label{10-8};
let Inst{7-0} = label{7-0};
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = 0b1000;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0;
}
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b1000;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0;
}
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = 0b1101;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0;
}
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b1101;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1101; // Rn = sp
let Inst{15} = 0;
}
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
UnOpFrag<(sextloadi8 node:$Src)>>;
-let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
- isCodeGenOnly = 1 in { // $dst doesn't exist in asmstring?
+let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
-def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
+def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
(ins t2addrmode_imm8s4:$addr),
- IIC_iLoad_d_i, "ldrd", "\t$dst1, $addr", []>;
-def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
- (ins i32imm:$addr), IIC_iLoad_d_i,
- "ldrd", "\t$dst1, $addr", []> {
- let Inst{19-16} = 0b1111; // Rn
-}
+ IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
// zextload i1 -> zextload i8
let Inst{20} = 1; // load
let Inst{11} = 1;
let Inst{10-8} = 0b110; // PUW.
-
+
bits<4> Rt;
bits<13> addr;
- let Inst{15-12} = Rt{3-0};
+ let Inst{15-12} = Rt;
let Inst{19-16} = addr{12-9};
let Inst{7-0} = addr{7-0};
}
BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
// Store doubleword
-let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
- isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
+let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
- (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
- IIC_iStore_d_r, "strd", "\t$src1, $addr", []>;
+ (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
+ IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
// Indexed stores
def t2STR_PRE : T2Iidxst<0, 0b10, 1, (outs GPR:$base_wb),
let Inst{20} = 0; // store
let Inst{11} = 1;
let Inst{10-8} = 0b110; // PUW
-
+
bits<4> Rt;
bits<13> addr;
- let Inst{15-12} = Rt{3-0};
+ let Inst{15-12} = Rt;
let Inst{19-16} = addr{12-9};
let Inst{7-0} = addr{7-0};
}
// ldrd / strd pre / post variants
// For disassembly only.
-def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2),
+def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
(ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
- "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>;
+ "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
-def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2),
+def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
(ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
- "ldrd", "\t$dst1, $dst2, [$base], $imm", []>;
+ "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs),
- (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
- IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base, $imm]!", []>;
+ (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
+ IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
- (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm),
- IIC_iStore_d_ru, "strd", "\t$src1, $src2, [$base], $imm", []>;
+ (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
+ IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
// data/instruction access. These are for disassembly only.
let Inst{21} = write;
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
-
+
bits<17> addr;
let Inst{19-16} = addr{16-13}; // Rn
let Inst{23} = addr{12}; // U
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
let Inst{11-8} = 0b1100;
-
+
bits<13> addr;
let Inst{19-16} = addr{12-9}; // Rn
let Inst{7-0} = addr{7-0}; // imm8
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
let Inst{11-6} = 0000000;
-
+
bits<10> addr;
let Inst{19-16} = addr{9-6}; // Rn
let Inst{3-0} = addr{5-2}; // Rm
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1111; // Rn
let Inst{14-12} = 0b000;
let Inst{7-4} = 0b0000;
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = 0b0010;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0;
}
bits<4> Rd;
bits<16> imm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{19-16} = imm{15-12};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
bits<4> Rd;
bits<16> imm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{19-16} = imm{15-12};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
bits<4> Rn;
bits<4> Rm;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
- let Inst{3-0} = Rm{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
+ let Inst{3-0} = Rm;
}
// Saturating add/subtract -- for disassembly only
bits<5> sat_imm;
bits<7> sh;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
let Inst{4-0} = sat_imm{4-0};
let Inst{21} = sh{6};
let Inst{14-12} = sh{4-2};
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010;
- let Inst{20} = ?; // The S bit.
let Inst{19-16} = 0b1111; // Rn
let Inst{14-12} = 0b000;
let Inst{7-4} = 0b0011;
bits<5> msb;
bits<5> lsb;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{4-0} = msb{4-0};
let Inst{14-12} = lsb{4-2};
let Inst{7-6} = lsb{1-0};
: T2BitFI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rn;
- let Inst{19-16} = Rn{3-0};
+ let Inst{19-16} = Rn;
}
let Constraints = "$src = $Rd" in
// Extra precision multiplies with low / high results
let neverHasSideEffects = 1 in {
let isCommutable = 1 in {
-def t2SMULL : T2FourReg<
+def t2SMULL : T2MulLong<
(outs rGPR:$Rd, rGPR:$Ra),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"smull", "\t$Rd, $Ra, $Rn, $Rm", []> {
let Inst{7-4} = 0b0000;
}
-def t2UMULL : T2FourReg<
- (outs rGPR:$Rd, rGPR:$Ra),
+def t2UMULL : T2MulLong<
+ (outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
- "umull", "\t$Rd, $Ra, $Rn, $Rm", []> {
+ "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
let Inst{22-20} = 0b010;
} // isCommutable
// Multiply + accumulate
-def t2SMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
+def t2SMLAL : T2MulLong<(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
- "smlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
+ "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>{
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
let Inst{22-20} = 0b100;
let Inst{7-4} = 0b0000;
}
-def t2UMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
+def t2UMLAL : T2MulLong<(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
- "umlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
+ "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>{
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
let Inst{22-20} = 0b110;
let Inst{7-4} = 0b0000;
}
-def t2UMAAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
+def t2UMAAL : T2MulLong<(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
- "umaal", "\t$Ra, $Rd, $Rn, $Rm", []>{
+ "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>{
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
let Inst{22-20} = 0b110;
let Inst{15-12} = 0b1111;
let Inst{7-6} = 0b10;
let Inst{5-4} = op2;
- let Rn{3-0} = Rm{3-0};
+ let Rn{3-0} = Rm;
}
def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
-defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
- IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
- BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
+
+def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_imm:$imm),
+ (t2CMPri GPR:$lhs, t2_so_imm:$imm)>;
+def : T2Pat<(ARMcmpZ GPR:$lhs, rGPR:$rhs),
+ (t2CMPrr GPR:$lhs, rGPR:$rhs)>;
+def : T2Pat<(ARMcmpZ GPR:$lhs, t2_so_reg:$rhs),
+ (t2CMPrs GPR:$lhs, t2_so_reg:$rhs)>;
//FIXME: Disable CMN, as CCodes are backwards from compare expectations
// Compare-to-zero still works out, just not the relationals
bits<4> Rd;
bits<16> imm;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
let Inst{19-16} = imm{15-12};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
bits<4> Rn;
bits<4> Rt;
- let Inst{19-16} = Rn{3-0};
- let Inst{15-12} = Rt{3-0};
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Rt;
}
class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
InstrItinClass itin, string opc, string asm, string cstr,
bits<4> Rd;
bits<4> Rn;
bits<4> Rt;
- let Inst{11-8} = Rd{3-0};
- let Inst{19-16} = Rn{3-0};
- let Inst{15-12} = Rt{3-0};
+ let Inst{11-8} = Rd;
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Rt;
}
let mayLoad = 1 in {
"ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
[], {?, ?, ?, ?}> {
bits<4> Rt2;
- let Inst{11-8} = Rt2{3-0};
+ let Inst{11-8} = Rt2;
}
}
"strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
{?, ?, ?, ?}> {
bits<4> Rt2;
- let Inst{11-8} = Rt2{3-0};
+ let Inst{11-8} = Rt2;
}
}
let Inst{31-27} = 0b11110;
let Inst{15-14} = 0b10;
let Inst{12} = 0;
-
+
bits<20> target;
let Inst{26} = target{19};
let Inst{11} = target{18};
bits<4> cc;
bits<4> mask;
- let Inst{7-4} = cc{3-0};
- let Inst{3-0} = mask{3-0};
+ let Inst{7-4} = cc;
+ let Inst{3-0} = mask;
}
// Branch and Exchange Jazelle -- for disassembly only
let Inst{25-20} = 0b111100;
let Inst{15-14} = 0b10;
let Inst{12} = 0;
-
+
bits<4> func;
- let Inst{19-16} = func{3-0};
+ let Inst{19-16} = func;
}
// Change Processor State is a system instruction -- for disassembly only.
let Inst{25-20} = 0b111010;
let Inst{15-14} = 0b10;
let Inst{12} = 0;
-
+
bits<11> opt;
-
+
// mode number
let Inst{4-0} = opt{4-0};
-
+
// M flag
let Inst{8} = opt{5};
-
+
// F flag
let Inst{5} = opt{6};
-
+
// I flag
let Inst{6} = opt{7};
-
+
// A flag
let Inst{7} = opt{8};
-
+
// imod flag
let Inst{10-9} = opt{10-9};
}
let Inst{12} = 0;
let Inst{10-8} = 0b000;
let Inst{7-4} = 0b1111;
-
+
bits<4> opt;
- let Inst{3-0} = opt{3-0};
+ let Inst{3-0} = opt;
}
// Secure Monitor Call is a system instruction -- for disassembly only
let Inst{31-27} = 0b11110;
let Inst{26-20} = 0b1111111;
let Inst{15-12} = 0b1000;
-
+
bits<4> opt;
- let Inst{19-16} = opt{3-0};
+ let Inst{19-16} = opt;
}
-class T2SRS<bits<12> op31_20,
+class T2SRS<bits<12> op31_20,
dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
let Inst{31-20} = op31_20{11-0};
-
+
bits<5> mode;
let Inst{4-0} = mode{4-0};
}
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
let Inst{31-20} = op31_20{11-0};
-
+
bits<4> Rn;
- let Inst{19-16} = Rn{3-0};
+ let Inst{19-16} = Rn;
}
def t2RFEDBW : T2RFE<0b111010000011,
string opc, string asm, list<dag> pattern>
: T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
- let Inst{11-8} = Rd{3-0};
+ let Inst{11-8} = Rd;
}
def t2MRS : T2MRS<0b111100111110, 0b10, 0,
: T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
bits<4> Rn;
bits<4> mask;
- let Inst{19-16} = Rn{3-0};
- let Inst{11-8} = mask{3-0};
+ let Inst{19-16} = Rn;
+ let Inst{11-8} = mask;
}
def t2MSR : T2MSR<0b111100111000, 0b10, 0,