//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
//===----------------------------------------------------------------------===//
-// Instructions
+// Instruction Class Templates
//===----------------------------------------------------------------------===//
-
class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
let Namespace = "ARM";
let Pattern = pattern;
}
+class IntBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
+
+class FPBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
+
+class DFPBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
+
+class Addr1BinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
def brtarget : Operand<OtherVT>;
// Operand for printing out a condition code.
def bx: InstARM<(ops), "bx r14", [(retflag)]>;
}
-let Defs = [R0, R1, R2, R3, R14] in {
- def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
+ def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
}
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
"ldr $dst, $addr",
[(set IntRegs:$dst, (load iaddr:$addr))]>;
+def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrb $dst, [$addr]",
+ [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
+
+def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrsb $dst, [$addr]",
+ [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
+
+def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrh $dst, [$addr]",
+ [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
+
+def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrsh $dst, [$addr]",
+ [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
+
def str : InstARM<(ops IntRegs:$src, memri:$addr),
"str $src, $addr",
[(store IntRegs:$src, iaddr:$addr)]>;
def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
-def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "add $dst, $a, $b",
- [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
-
-def ADCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "adcs $dst, $a, $b",
- [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
-
-def ADDS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "adds $dst, $a, $b",
- [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
+def ADD : Addr1BinOp<"add", add>;
+def ADCS : Addr1BinOp<"adcs", adde>;
+def ADDS : Addr1BinOp<"adds", addc>;
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
[(set IntRegs:$dst, iaddr:$addr)]>;
-def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "sub $dst, $a, $b",
- [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
-
-def SBCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "sbcs $dst, $a, $b",
- [(set IntRegs:$dst, (sube IntRegs:$a, addr_mode1:$b))]>;
-
-def SUBS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "subs $dst, $a, $b",
- [(set IntRegs:$dst, (subc IntRegs:$a, addr_mode1:$b))]>;
-
-def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "and $dst, $a, $b",
- [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
-
-def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "eor $dst, $a, $b",
- [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
-
-def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "orr $dst, $a, $b",
- [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
+def SUB : Addr1BinOp<"sub", sub>;
+def SBCS : Addr1BinOp<"sbcs", sube>;
+def SUBS : Addr1BinOp<"subs", subc>;
+def AND : Addr1BinOp<"and", and>;
+def EOR : Addr1BinOp<"eor", xor>;
+def ORR : Addr1BinOp<"orr", or>;
let isTwoAddress = 1 in {
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
IntRegs:$false, imm:$cc))]>;
}
-def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "mul $dst, $a, $b",
- [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
+def MUL : IntBinOp<"mul", mul>;
let Defs = [R0] in {
- def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "smull r12, $dst, $a, $b",
- [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>;
-
- def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "umull r12, $dst, $a, $b",
- [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>;
+ def SMULL : IntBinOp<"smull r12,", mulhs>;
+ def UMULL : IntBinOp<"umull r12,", mulhu>;
}
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
"fcmpd $a, $b",
[(armcmp DFPRegs:$a, DFPRegs:$b)]>;
+// Floating Point Copy
+def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
+
+def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
+
// Floating Point Conversion
// We use bitconvert for moving the data between the register classes.
// The format conversion is done with ARM specific nodes
def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
// Floating Point Arithmetic
-def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
- "fadds $dst, $a, $b",
- [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
-
-def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
- "faddd $dst, $a, $b",
- [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
-
-def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
- "fsubs $dst, $a, $b",
- [(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>;
-
-def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
- "fsubd $dst, $a, $b",
- [(set DFPRegs:$dst, (fsub DFPRegs:$a, DFPRegs:$b))]>;
+def FADDS : FPBinOp<"fadds", fadd>;
+def FADDD : DFPBinOp<"faddd", fadd>;
+def FSUBS : FPBinOp<"fsubs", fsub>;
+def FSUBD : DFPBinOp<"fsubd", fsub>;
def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
"fnegs $dst, $src",
"fnegd $dst, $src",
[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
-def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
- "fmuls $dst, $a, $b",
- [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
-
-def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
- "fmuld $dst, $a, $b",
- [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
-
+def FMULS : FPBinOp<"fmuls", fmul>;
+def FMULD : DFPBinOp<"fmuld", fmul>;
+def FDIVS : FPBinOp<"fdivs", fdiv>;
+def FDIVD : DFPBinOp<"fdivd", fdiv>;
// Floating Point Load
def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
"fldd $dst, $addr",
[(set DFPRegs:$dst, (load IntRegs:$addr))]>;
+
+def : Pat<(ARMcall tglobaladdr:$dst),
+ (bl tglobaladdr:$dst)>;
+
+def : Pat<(ARMcall texternalsym:$dst),
+ (bl texternalsym:$dst)>;
projects / oota-llvm.git / blobdiff