// Define ARM specific addressing mode.
//Addressing Mode 1: data processing operands
-def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl]>;
+def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
+ []>;
//register plus/minus 12 bit offset
-def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
+def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
//register plus scaled register
-//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
+//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
//===----------------------------------------------------------------------===//
-// Instructions
+// Instruction Class Templates
//===----------------------------------------------------------------------===//
-
class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
let Namespace = "ARM";
let Pattern = pattern;
}
+class IntBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
+
+class FPBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
+
+class DFPBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
+
+class Addr1BinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
def brtarget : Operand<OtherVT>;
// Operand for printing out a condition code.
[SDNPHasChain, SDNPOptInFlag]>;
def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
-
def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
+def SDTarmfmstat : SDTypeProfile<0, 0, []>;
+def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
+
def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
-def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
+def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
+def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
+def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
+def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
+def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
+def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
+def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
- [(callseq_end imm:$amt)]>;
+ [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
let isReturn = 1 in {
def bx: InstARM<(ops), "bx r14", [(retflag)]>;
}
-let Defs = [R0, R1, R2, R3, R14] in {
- def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
+ def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
}
def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
"ldr $dst, $addr",
[(set IntRegs:$dst, (load iaddr:$addr))]>;
+def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrb $dst, [$addr]",
+ [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
+
+def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrsb $dst, [$addr]",
+ [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
+
+def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrh $dst, [$addr]",
+ [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
+
+def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+ "ldrsh $dst, [$addr]",
+ [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
+
def str : InstARM<(ops IntRegs:$src, memri:$addr),
"str $src, $addr",
[(store IntRegs:$src, iaddr:$addr)]>;
def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
-def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "add $dst, $a, $b",
- [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
+def ADD : Addr1BinOp<"add", add>;
+def ADCS : Addr1BinOp<"adcs", adde>;
+def ADDS : Addr1BinOp<"adds", addc>;
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
[(set IntRegs:$dst, iaddr:$addr)]>;
-def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "sub $dst, $a, $b",
- [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
-
-def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "and $dst, $a, $b",
- [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
-
-def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "eor $dst, $a, $b",
- [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
-
-def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
- "orr $dst, $a, $b",
- [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
+def SUB : Addr1BinOp<"sub", sub>;
+def SBCS : Addr1BinOp<"sbcs", sube>;
+def SUBS : Addr1BinOp<"subs", subc>;
+def AND : Addr1BinOp<"and", and>;
+def EOR : Addr1BinOp<"eor", xor>;
+def ORR : Addr1BinOp<"orr", or>;
let isTwoAddress = 1 in {
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
IntRegs:$false, imm:$cc))]>;
}
-def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "mul $dst, $a, $b",
- [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
+def MUL : IntBinOp<"mul", mul>;
+
+let Defs = [R0] in {
+ def SMULL : IntBinOp<"smull r12,", mulhs>;
+ def UMULL : IntBinOp<"umull r12,", mulhu>;
+}
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
"b$cc $dst",
"cmp $a, $b",
[(armcmp IntRegs:$a, addr_mode1:$b)]>;
+// Floating Point Compare
+def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
+ "fcmps $a, $b",
+ [(armcmp FPRegs:$a, FPRegs:$b)]>;
+
+def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
+ "fcmpd $a, $b",
+ [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
+
+// Floating Point Copy
+def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
+
+def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
// Floating Point Conversion
// We use bitconvert for moving the data between the register classes.
def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
"fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
+def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+ "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
+
def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
"fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
+def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+ "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
-// Floating Point Arithmetic
-def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
- "fadds $dst, $a, $b",
- [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
+def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+ "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
+
+def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+ "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
-def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
- "faddd $dst, $a, $b",
- [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
+def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
+ "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
-def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
- "fmuls $dst, $a, $b",
- [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
+def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+ "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
-def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
- "fmuld $dst, $a, $b",
- [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
+def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
+ "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
+def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+ "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
+
+def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
+
+// Floating Point Arithmetic
+def FADDS : FPBinOp<"fadds", fadd>;
+def FADDD : DFPBinOp<"faddd", fadd>;
+def FSUBS : FPBinOp<"fsubs", fsub>;
+def FSUBD : DFPBinOp<"fsubd", fsub>;
+
+def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+ "fnegs $dst, $src",
+ [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
+
+def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
+ "fnegd $dst, $src",
+ [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
+
+def FMULS : FPBinOp<"fmuls", fmul>;
+def FMULD : DFPBinOp<"fmuld", fmul>;
+def FDIVS : FPBinOp<"fdivs", fdiv>;
+def FDIVD : DFPBinOp<"fdivd", fdiv>;
// Floating Point Load
def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
"fldd $dst, $addr",
[(set DFPRegs:$dst, (load IntRegs:$addr))]>;
+
+def : Pat<(ARMcall tglobaladdr:$dst),
+ (bl tglobaladdr:$dst)>;
+
+def : Pat<(ARMcall texternalsym:$dst),
+ (bl texternalsym:$dst)>;
projects / oota-llvm.git / blobdiff