expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS

[oota-llvm.git] / lib / Target / ARM / ARMInstrInfo.td

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index cacff859af2b5e8f472c64f0d3dcac20346ad24a..ca3d1c2aecba91b040cd21526480fad380d005a0 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -128,8 +128,8 @@ let isReturn = 1 in {
   def bx: InstARM<(ops), "bx r14", [(retflag)]>;
 }
 
-let  Defs = [R0, R1, R2, R3, R14] in {
-  def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
+  def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
 }
 
 def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
@@ -286,3 +286,9 @@ def FLDS  : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
 def FLDD  : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
                      "fldd $dst, $addr",
                      [(set DFPRegs:$dst, (load IntRegs:$addr))]>;
+
+def : Pat<(ARMcall tglobaladdr:$dst),
+          (bl tglobaladdr:$dst)>;
+
+def : Pat<(ARMcall texternalsym:$dst),
+          (bl texternalsym:$dst)>;