The ARM instructions that have an unpredictable behavior when the pc register operand...

[oota-llvm.git] / lib / Target / ARM / ARMInstrInfo.td

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3b647cdee224838d8d8b8c860cf17a30aba31912..a594271c94eace2e9523c07bb3de832de020f967 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -4128,8 +4128,8 @@ multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
     let Inst{3-0} = shift{3-0};
   }
 
-  def rsr : AsI1<opcod, (outs GPR:$Rd),
-               (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
+  def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
+               (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
                iis, opc, "\t$Rd, $Rn, $shift", []>,
                RegConstraint<"$Rn = $Rd"> {
     bits<4> Rd;