Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work

[oota-llvm.git] / lib / Target / ARM / ARMInstrInfo.td

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3c1da1efb6523646d0dfc4ad5f5031ebf0c691fe..95ab0f1d8d6c5b669265a5522465bebf244caf48 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -398,7 +398,7 @@ def addrmode_imm12 : Operand<i32>,
   // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
   // immediate values are as normal.
 
-  string EncoderMethod = "getAddrModeImm12OpValue";
+  string EncoderMethod = "getAddrModeImmOpValue";
   let PrintMethod = "printAddrModeImm12Operand";
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
 }
@@ -464,6 +464,7 @@ def addrmode5 : Operand<i32>,
   let PrintMethod = "printAddrMode5Operand";
   let MIOperandInfo = (ops GPR:$base, i32imm);
   let ParserMatchClass = ARMMemMode5AsmOperand;
+  string EncoderMethod = "getAddrModeImmOpValue";
 }
 
 // addrmode6 := reg with optional writeback
@@ -830,9 +831,9 @@ multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
                    AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
                   [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
     bits<4> Rt;
-    bits<17> addr;
-    let Inst{23}    = addr{12};     // U (add = ('U' == 1))
-    let Inst{19-16} = addr{16-13};  // Rn
+    bits<32> addr;
+    let Inst{23}    = addr{16};     // U (add = ('U' == 1))
+    let Inst{19-16} = addr{20-17};  // Rn
     let Inst{15-12} = Rt;
     let Inst{11-0}  = addr{11-0};   // imm12
   }
@@ -840,9 +841,9 @@ multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
                   AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
                  [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
     bits<4> Rt;
-    bits<17> shift;
-    let Inst{23}    = shift{12};    // U (add = ('U' == 1))
-    let Inst{19-16} = shift{16-13}; // Rn
+    bits<32> shift;
+    let Inst{23}    = shift{16};    // U (add = ('U' == 1))
+    let Inst{19-16} = shift{20-17}; // Rn
     let Inst{11-0}  = shift{11-0};
   }
 }