Move duplicated AddLiveIn function from X86 and ARM backends to be a method

[oota-llvm.git] / lib / Target / ARM / ARMISelLowering.cpp

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 446326d5e6fae5738376677352e74f62a979502e..e35b6672a3152186f07b11ef85b93866e5011ce6 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -405,25 +405,24 @@ static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                                         ARM::R3,
                                         ARM::NoRegister };
 
-  if (unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4)) {
-    unsigned i;
-    for (i = 0; i < 4; ++i)
-      if (HiRegList[i] == Reg)
-        break;
+  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4);
+  if (Reg == 0) 
+    return false; // we didn't handle it
 
-    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
-                                           MVT::i32, LocInfo));
-    if (LoRegList[i] != ARM::NoRegister)
-      State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
-                                             MVT::i32, LocInfo));
-    else
-      State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
-                                             State.AllocateStack(4, 4),
-                                             MVT::i32, LocInfo));
-    return true;  // we handled it
-  }
+  unsigned i;
+  for (i = 0; i < 4; ++i)
+    if (HiRegList[i] == Reg)
+      break;
 
-  return false; // we didn't handle it
+  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
+  if (LoRegList[i] != ARM::NoRegister)
+    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
+                                           MVT::i32, LocInfo));
+  else
+    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
+                                           State.AllocateStack(4, 4),
+                                           MVT::i32, LocInfo));
+  return true;  // we handled it
 }
 
 // AAPCS f64 is in aligned register pairs
@@ -434,20 +433,19 @@ static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
   static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
   static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
 
-  if (unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2)) {
-    unsigned i;
-    for (i = 0; i < 2; ++i)
-      if (HiRegList[i] == Reg)
-        break;
+  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
+  if (Reg == 0)
+    return false; // we didn't handle it
 
-    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
-                                           MVT::i32, LocInfo));
-    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
-                                           MVT::i32, LocInfo));
-    return true;  // we handled it
-  }
+  unsigned i;
+  for (i = 0; i < 2; ++i)
+    if (HiRegList[i] == Reg)
+      break;
 
-  return false; // we didn't handle it
+  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
+  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
+                                         MVT::i32, LocInfo));
+  return true;  // we handled it
 }
 
 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
@@ -457,20 +455,19 @@ static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
   static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
   static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
 
-  if (unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2)) {
-    unsigned i;
-    for (i = 0; i < 2; ++i)
-      if (HiRegList[i] == Reg)
-        break;
+  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
+  if (Reg == 0)
+    return false; // we didn't handle it
 
-    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
-                                           MVT::i32, LocInfo));
-    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
-                                           MVT::i32, LocInfo));
-    return true;  // we handled it
-  }
+  unsigned i;
+  for (i = 0; i < 2; ++i)
+    if (HiRegList[i] == Reg)
+      break;
 
-  return false; // we didn't handle it
+  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
+  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
+                                         MVT::i32, LocInfo));
+  return true;  // we handled it
 }
 
 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
@@ -481,17 +478,6 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                                    State);
 }
 
-/// AddLiveIn - This helper function adds the specified physical register to the
-/// MachineFunction as a live in value.  It also creates a corresponding virtual
-/// register for it.
-static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
-                          const TargetRegisterClass *RC) {
-  assert(RC->contains(PReg) && "Not the correct regclass!");
-  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
-  MF.getRegInfo().addLiveIn(PReg, VReg);
-  return VReg;
-}
-
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 /// appropriate copies out of appropriate physical registers.  This assumes that
 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
@@ -1104,7 +1090,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
         assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
 
       // Transform the arguments stored in physical registers into virtual ones.
-      unsigned Reg = AddLiveIn(MF, VA.getLocReg(), RC);
+      unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
       SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
 
       // f64 is passed in i32 pairs and must be combined.
@@ -1121,7 +1107,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
           SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
           ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
         } else {
-          Reg = AddLiveIn(MF, VA.getLocReg(), RC);
+          Reg = MF.addLiveIn(VA.getLocReg(), RC);
           ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
         }
 
@@ -1198,7 +1184,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
         else
           RC = ARM::GPRRegisterClass;
 
-        unsigned VReg = AddLiveIn(MF, GPRArgRegs[NumGPRs], RC);
+        unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
         SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
         SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
         MemOps.push_back(Store);